From 17ff2b3a870ff3be68952e69bc8557963965e742 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Thu, 31 Mar 2005 02:05:53 +0000 Subject: [PATCH] Pass the correct values to the chain argument for node construction during LowerCallTo. Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for loads and stores, amazing! llvm-svn: 20946 --- lib/Target/PowerPC/PPC32ISelPattern.cpp | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/lib/Target/PowerPC/PPC32ISelPattern.cpp b/lib/Target/PowerPC/PPC32ISelPattern.cpp index e3803b9f141..bfb03275eb8 100644 --- a/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -321,21 +321,22 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, case MVT::f64: if (FPR_remaining > 0) { if (isVarArg) { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff)); + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, + Args[i].first, PtrOff); + MemOps.push_back(Store); // Float varargs are always shadowed in available integer registers if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff); MemOps.push_back(Load); - args_to_use.push_back(DAG.getCopyToReg(Chain, Load, + args_to_use.push_back(DAG.getCopyToReg(Load, Load, GPR[GPR_idx])); } if (GPR_remaining > 1 && MVT::f64 == ArgVT) { SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff); MemOps.push_back(Load); - args_to_use.push_back(DAG.getCopyToReg(Chain, Load, + args_to_use.push_back(DAG.getCopyToReg(Load, Load, GPR[GPR_idx+1])); } } @@ -521,6 +522,13 @@ unsigned ISel::getGlobalBaseReg() { //Check to see if the load is a constant offset from a base register void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset) { + unsigned imm = 0, opcode = N.getOpcode(); + if (N.getOpcode() == ISD::ADD) + if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, imm)) { + Reg = SelectExpr(N.getOperand(0)); + offset = imm; + return; + } Reg = SelectExpr(N); offset = 0; return;