From 1bcff610040ba72d7f76255315f31591c538fc09 Mon Sep 17 00:00:00 2001
From: Zaara Syeda <syzaara@ca.ibm.com>
Date: Mon, 5 Nov 2018 17:31:26 +0000
Subject: [PATCH] [Power9] Add support for stxvw4x.be and stxvd2x.be intrinsics

On Power9, we don't have patterns to select the following intrinsics:
llvm.ppc.vsx.stxvw4x.be
llvm.ppc.vsx.stxvd2x.be

This patch adds support for these.

Differential Revision: https://reviews.llvm.org/D53581

llvm-svn: 346148
---
 lib/Target/PowerPC/PPCInstrVSX.td    |  8 ++--
 test/CodeGen/PowerPC/vsx.ll          | 48 ------------------------
 test/CodeGen/PowerPC/vsx_builtins.ll | 56 ++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 52 deletions(-)
 create mode 100644 test/CodeGen/PowerPC/vsx_builtins.ll

diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td
index 6a4586002b2..9d462df6fef 100644
--- a/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1066,10 +1066,6 @@ let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
   // Stores.
   def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
             (STXVD2X $rS, xoaddr:$dst)>;
-  def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, xoaddr:$dst),
-            (STXVD2X $rS, xoaddr:$dst)>;
-  def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, xoaddr:$dst),
-            (STXVW4X $rS, xoaddr:$dst)>;
   def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
 }
 let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
@@ -1990,6 +1986,10 @@ let Predicates = [IsLittleEndian, HasVSX] in
   def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
             (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>;
 
+def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, xoaddr:$dst),
+            (STXVD2X $rS, xoaddr:$dst)>;
+def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, xoaddr:$dst),
+            (STXVW4X $rS, xoaddr:$dst)>;
 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
 
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index 3df501db41f..d6a5ed37040 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -1211,51 +1211,3 @@ entry:
 ; CHECK-LE: xscmpudp cr0, f3, f4
 ; CHECK-LE: beqlr cr0
 }
-
-; Function Attrs: nounwind readnone
-define <4 x i32> @test83(i8* %a) {
-  entry:
-    %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
-      ret <4 x i32> %0
-; CHECK-LABEL: test83
-; CHECK: lxvw4x v2, 0, r3
-; CHECK: blr
-}
-; Function Attrs: nounwind readnone
-declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
-
-; Function Attrs: nounwind readnone
-define <2 x double> @test84(i8* %a) {
-  entry:
-    %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
-      ret <2 x double> %0
-; CHECK-LABEL: test84
-; CHECK: lxvd2x v2, 0, r3
-; CHECK: blr
-}
-; Function Attrs: nounwind readnone
-declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
-
-; Function Attrs: nounwind readnone
-define void @test85(<4 x i32> %a, i8* %b) {
-  entry:
-    tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
-    ret void
-; CHECK-LABEL: test85
-; CHECK: stxvw4x v2, 0, r5
-; CHECK: blr
-}
-; Function Attrs: nounwind readnone
-declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
-
-; Function Attrs: nounwind readnone
-define void @test86(<2 x double> %a, i8* %b) {
-  entry:
-    tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
-    ret void
-; CHECK-LABEL: test86
-; CHECK: stxvd2x v2, 0, r5
-; CHECK: blr
-}
-; Function Attrs: nounwind readnone
-declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
diff --git a/test/CodeGen/PowerPC/vsx_builtins.ll b/test/CodeGen/PowerPC/vsx_builtins.ll
new file mode 100644
index 00000000000..b386565500f
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx_builtins.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \
+; RUN:     -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @test1(i8* %a) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvw4x v2, 0, r3
+; CHECK-NEXT:    blr
+  entry:
+    %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
+      ret <4 x i32> %0
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
+
+; Function Attrs: nounwind readnone
+define <2 x double> @test2(i8* %a) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvd2x v2, 0, r3
+; CHECK-NEXT:    blr
+  entry:
+    %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
+      ret <2 x double> %0
+}
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
+
+; Function Attrs: nounwind readnone
+define void @test3(<4 x i32> %a, i8* %b) {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvw4x v2, 0, r5
+; CHECK-NEXT:    blr
+  entry:
+    tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
+    ret void
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
+
+; Function Attrs: nounwind readnone
+define void @test4(<2 x double> %a, i8* %b) {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvd2x v2, 0, r5
+; CHECK-NEXT:    blr
+  entry:
+    tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
+    ret void
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)