From 269811ad82dfa6975cf0da26c44800c5d052013f Mon Sep 17 00:00:00 2001 From: Marina Yatsina Date: Wed, 28 Sep 2016 15:52:56 +0000 Subject: [PATCH] [x86] Accept 'retn' as an alias to 'ret[lqw]'\'ret' (At&t\Intel) Implement 'retn' simply by aliasing it to the relevant 'ret' instruction Commit on behalf of coby Differential Revision: https://reviews.llvm.org/D24346 llvm-svn: 282601 --- lib/Target/X86/X86InstrInfo.td | 6 ++++++ test/MC/X86/ret.s | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index f2474df7130..3cbcfa6c723 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2630,6 +2630,12 @@ def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + def : MnemonicAlias<"sal", "shl", "intel">; def : MnemonicAlias<"salb", "shlb", "att">; def : MnemonicAlias<"salw", "shlw", "att">; diff --git a/test/MC/X86/ret.s b/test/MC/X86/ret.s index bac669b2561..142a4614ba4 100644 --- a/test/MC/X86/ret.s +++ b/test/MC/X86/ret.s @@ -57,6 +57,22 @@ // ERR32: error: instruction requires: 64-bit mode // ERR16: error: instruction requires: 64-bit mode + retn +// 64: retq +// 64: encoding: [0xc3] +// 32: retl +// 32: encoding: [0xc3] +// 16: retw +// 16: encoding: [0xc3] + + retn $0 +// 64: retq $0 +// 64: encoding: [0xc2,0x00,0x00] +// 32: retl $0 +// 32: encoding: [0xc2,0x00,0x00] +// 16: retw $0 +// 16: encoding: [0xc2,0x00,0x00] + lret // 64: lretl // 64: encoding: [0xcb]