From 297e39ba1f27566e5ab97162c4e59aec9339e501 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 28 May 2019 19:37:09 +0000 Subject: [PATCH] [AMDGPU] Correct the handling of inlineasm output registers. Summary: - There's a regression due to the cross-block RC assignment. Use the proper way to derive the output register RC in inline asm. Reviewers: rampitec, alex-t Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, eraman, hiraditya, llvm-commits, yaxunl Tags: #llvm Differential Revision: https://reviews.llvm.org/D62537 llvm-svn: 361868 --- lib/Target/AMDGPU/SIISelLowering.cpp | 3 +-- test/CodeGen/AMDGPU/inline-asm.ll | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 8f93c63046c..c860d3ae06c 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10244,8 +10244,7 @@ bool SITargetLowering::requiresUniformRegister(MachineFunction &MF, unsigned AssignedReg; const TargetRegisterClass *RC; std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint( - SIRI, TC.ConstraintCode, - getSimpleValueType(MF.getDataLayout(), CS.getType())); + SIRI, TC.ConstraintCode, TC.ConstraintVT); if (RC) { MachineRegisterInfo &MRI = MF.getRegInfo(); if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) diff --git a/test/CodeGen/AMDGPU/inline-asm.ll b/test/CodeGen/AMDGPU/inline-asm.ll index 6a97626c7b0..a964dedb271 100644 --- a/test/CodeGen/AMDGPU/inline-asm.ll +++ b/test/CodeGen/AMDGPU/inline-asm.ll @@ -277,3 +277,23 @@ entry: tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> ) #1 ret void } + +; Check aggregate types are handled properly. +; CHECK-LABEL: mad_u64 +; CHECK: v_mad_u64_u32 +define void @mad_u64(i32 %x) { +entry: + br i1 undef, label %exit, label %false + +false: + %s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0) + br label %exit + +exit: + %s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false] + %v0 = extractvalue { i64, i64 } %s1, 0 + %v1 = extractvalue { i64, i64 } %s1, 1 + tail call void asm sideeffect "; use $0", "v"(i64 %v0) + tail call void asm sideeffect "; use $0", "v"(i64 %v1) + ret void +}