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[AArch64] Fix miscompile of comparison with 0xffffffffffffffff
Some literals in the AArch64 backend had 15 'f's rather than 16, causing comparisons with a constant 0xffffffffffffffff to be miscompiled. llvm-svn: 221157
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@ -1158,9 +1158,9 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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break;
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case ISD::SETLE:
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case ISD::SETGT:
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if ((VT == MVT::i32 && C != 0x7fffffff &&
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if ((VT == MVT::i32 && C != INT32_MAX &&
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isLegalArithImmed((uint32_t)(C + 1))) ||
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(VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
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(VT == MVT::i64 && C != INT64_MAX &&
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isLegalArithImmed(C + 1ULL))) {
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CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
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C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
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@ -1169,9 +1169,9 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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break;
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case ISD::SETULE:
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case ISD::SETUGT:
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if ((VT == MVT::i32 && C != 0xffffffff &&
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if ((VT == MVT::i32 && C != UINT32_MAX &&
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isLegalArithImmed((uint32_t)(C + 1))) ||
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(VT == MVT::i64 && C != 0xfffffffffffffffULL &&
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(VT == MVT::i64 && C != UINT64_MAX &&
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isLegalArithImmed(C + 1ULL))) {
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CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
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C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
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36
test/CodeGen/AArch64/cmp-const-max.ll
Normal file
36
test/CodeGen/AArch64/cmp-const-max.ll
Normal file
@ -0,0 +1,36 @@
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; RUN: llc -verify-machineinstrs -aarch64-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
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define i32 @ule_64_max(i64 %p) {
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entry:
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; CHECK-LABEL: ule_64_max:
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; CHECK: cmn x0, #1
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; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
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%cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff
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br i1 %cmp, label %ret_one, label %ret_zero
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ret_one:
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ret i32 1
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ret_zero:
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; CHECK: [[RET_ZERO]]:
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; CHECK-NEXT: mov w0, wzr
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ret i32 0
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}
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define i32 @ugt_64_max(i64 %p) {
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entry:
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; CHECK-LABEL: ugt_64_max:
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; CHECK: cmn x0, #1
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; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
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%cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff
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br i1 %cmp, label %ret_one, label %ret_zero
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ret_one:
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ret i32 1
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ret_zero:
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; CHECK: [[RET_ZERO]]:
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; CHECK-NEXT: mov w0, wzr
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ret i32 0
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}
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