[AArch64] Fix miscompile of comparison with 0xffffffffffffffff

Some literals in the AArch64 backend had 15 'f's rather than 16, causing
comparisons with a constant 0xffffffffffffffff to be miscompiled.

llvm-svn: 221157
This commit is contained in:
Oliver Stannard 2014-11-03 15:28:40 +00:00
parent f60eba6543
commit 2c73f413f7
2 changed files with 40 additions and 4 deletions

View File

@ -1158,9 +1158,9 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
break;
case ISD::SETLE:
case ISD::SETGT:
if ((VT == MVT::i32 && C != 0x7fffffff &&
if ((VT == MVT::i32 && C != INT32_MAX &&
isLegalArithImmed((uint32_t)(C + 1))) ||
(VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
(VT == MVT::i64 && C != INT64_MAX &&
isLegalArithImmed(C + 1ULL))) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
@ -1169,9 +1169,9 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
break;
case ISD::SETULE:
case ISD::SETUGT:
if ((VT == MVT::i32 && C != 0xffffffff &&
if ((VT == MVT::i32 && C != UINT32_MAX &&
isLegalArithImmed((uint32_t)(C + 1))) ||
(VT == MVT::i64 && C != 0xfffffffffffffffULL &&
(VT == MVT::i64 && C != UINT64_MAX &&
isLegalArithImmed(C + 1ULL))) {
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;

View File

@ -0,0 +1,36 @@
; RUN: llc -verify-machineinstrs -aarch64-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
define i32 @ule_64_max(i64 %p) {
entry:
; CHECK-LABEL: ule_64_max:
; CHECK: cmn x0, #1
; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
%cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff
br i1 %cmp, label %ret_one, label %ret_zero
ret_one:
ret i32 1
ret_zero:
; CHECK: [[RET_ZERO]]:
; CHECK-NEXT: mov w0, wzr
ret i32 0
}
define i32 @ugt_64_max(i64 %p) {
entry:
; CHECK-LABEL: ugt_64_max:
; CHECK: cmn x0, #1
; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
%cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff
br i1 %cmp, label %ret_one, label %ret_zero
ret_one:
ret i32 1
ret_zero:
; CHECK: [[RET_ZERO]]:
; CHECK-NEXT: mov w0, wzr
ret i32 0
}