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R600: Rely on TypeLegalizer to use divrem instead of div/rem
reviewer: tstellardAMD llvm-svn: 238337
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6d322a1035
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2fe80f46a3
@ -171,13 +171,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM,
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
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// These should be replaced by UDVIREM, but it does not happen automatically
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// during Type Legalization
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setOperationAction(ISD::UDIV, MVT::i64, Custom);
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setOperationAction(ISD::UREM, MVT::i64, Custom);
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setOperationAction(ISD::SDIV, MVT::i64, Custom);
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setOperationAction(ISD::SREM, MVT::i64, Custom);
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// We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
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// to be Legal/Custom in order to avoid library calls.
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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@ -879,42 +872,6 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(Result);
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return;
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}
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case ISD::UDIV: {
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SDValue Op = SDValue(N, 0);
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
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N->getOperand(0), N->getOperand(1));
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Results.push_back(UDIVREM);
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break;
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}
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case ISD::UREM: {
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SDValue Op = SDValue(N, 0);
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
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N->getOperand(0), N->getOperand(1));
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Results.push_back(UDIVREM.getValue(1));
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break;
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}
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case ISD::SDIV: {
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SDValue Op = SDValue(N, 0);
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
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N->getOperand(0), N->getOperand(1));
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Results.push_back(SDIVREM);
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break;
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}
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case ISD::SREM: {
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SDValue Op = SDValue(N, 0);
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
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N->getOperand(0), N->getOperand(1));
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Results.push_back(SDIVREM.getValue(1));
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break;
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}
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case ISD::SDIVREM: {
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SDValue Op = SDValue(N, 1);
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SDValue RES = LowerSDIVREM(Op, DAG);
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