From 34d22f34a85323fbcd81474547d4b1791ca11ef4 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sun, 3 May 2009 13:18:16 +0000
Subject: [PATCH] Properly handle sdiv / udiv / srem / urem libcalls

llvm-svn: 70764
---
 include/llvm/CodeGen/RuntimeLibcalls.h      |  4 ++++
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp    | 18 +++++++++++-------
 lib/CodeGen/SelectionDAG/TargetLowering.cpp |  4 ++++
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/include/llvm/CodeGen/RuntimeLibcalls.h b/include/llvm/CodeGen/RuntimeLibcalls.h
index 417f8d3f749..f7a8c7eecdc 100644
--- a/include/llvm/CodeGen/RuntimeLibcalls.h
+++ b/include/llvm/CodeGen/RuntimeLibcalls.h
@@ -45,15 +45,19 @@ namespace RTLIB {
     MUL_I32,
     MUL_I64,
     MUL_I128,
+    SDIV_I16,
     SDIV_I32,
     SDIV_I64,
     SDIV_I128,
+    UDIV_I16,
     UDIV_I32,
     UDIV_I64,
     UDIV_I128,
+    SREM_I16,
     SREM_I32,
     SREM_I64,
     SREM_I128,
+    UREM_I16,
     UREM_I32,
     UREM_I64,
     UREM_I128,
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 98908765b73..bdcad0a3b5e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3308,16 +3308,20 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       switch (Node->getOpcode()) {
       case ISD::UDIV:
       case ISD::SDIV:
-        if (VT == MVT::i32) {
-          LC = Node->getOpcode() == ISD::UDIV
-               ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
-          isSigned = Node->getOpcode() == ISD::SDIV;
-        }
-        break;
+       isSigned = Node->getOpcode() == ISD::SDIV;
+       if (VT == MVT::i16)
+         LC = (isSigned ? RTLIB::SDIV_I16  : RTLIB::UDIV_I16);
+       else if (VT == MVT::i32)
+         LC = (isSigned ? RTLIB::SDIV_I32  : RTLIB::UDIV_I32);
+       else if (VT == MVT::i64)
+         LC = (isSigned ? RTLIB::SDIV_I64  : RTLIB::UDIV_I64);
+       else if (VT == MVT::i128)
+         LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128);
+       break;
       case ISD::MUL:
         if (VT == MVT::i16)
           LC = RTLIB::MUL_I16;
-        if (VT == MVT::i32)
+        else if (VT == MVT::i32)
           LC = RTLIB::MUL_I32;
         else if (VT == MVT::i64)
           LC = RTLIB::MUL_I64;
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 959274789c7..8eb4de4655a 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -67,15 +67,19 @@ static void InitLibcallNames(const char **Names) {
   Names[RTLIB::MUL_I32] = "__mulsi3";
   Names[RTLIB::MUL_I64] = "__muldi3";
   Names[RTLIB::MUL_I128] = "__multi3";
+  Names[RTLIB::SDIV_I16] = "__divhi3";
   Names[RTLIB::SDIV_I32] = "__divsi3";
   Names[RTLIB::SDIV_I64] = "__divdi3";
   Names[RTLIB::SDIV_I128] = "__divti3";
+  Names[RTLIB::UDIV_I32] = "__udivhi3";
   Names[RTLIB::UDIV_I32] = "__udivsi3";
   Names[RTLIB::UDIV_I64] = "__udivdi3";
   Names[RTLIB::UDIV_I128] = "__udivti3";
+  Names[RTLIB::SREM_I16] = "__modhi3";
   Names[RTLIB::SREM_I32] = "__modsi3";
   Names[RTLIB::SREM_I64] = "__moddi3";
   Names[RTLIB::SREM_I128] = "__modti3";
+  Names[RTLIB::UREM_I16] = "__umodsi3";
   Names[RTLIB::UREM_I32] = "__umodsi3";
   Names[RTLIB::UREM_I64] = "__umoddi3";
   Names[RTLIB::UREM_I128] = "__umodti3";