From 3f664b6fd3896111ee2d45881395f36df43a446a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 30 Jun 2008 20:45:06 +0000 Subject: [PATCH] Split scheduling from instruction selection. llvm-svn: 52923 --- include/llvm/CodeGen/SelectionDAGISel.h | 12 +++++---- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 14 +++++++--- lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 ++--- lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 11 +++----- lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 11 +++----- lib/Target/IA64/IA64ISelDAGToDAG.cpp | 11 +++----- lib/Target/Mips/MipsISelDAGToDAG.cpp | 9 +++---- lib/Target/PIC16/PIC16ISelDAGToDAG.cpp | 9 +++---- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 11 +++----- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 11 +++----- lib/Target/X86/X86ISelDAGToDAG.cpp | 27 +++++++++++-------- 11 files changed, 62 insertions(+), 70 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 54b4accd425..7925a007922 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -58,7 +58,9 @@ public: unsigned MakeReg(MVT VT); virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} - virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0; + virtual void InstructionSelect(SelectionDAG &SD) = 0; + virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {} + virtual void SelectRootInit() { DAGSize = CurDAG->AssignTopologicalOrder(TopOrder); } @@ -160,10 +162,6 @@ public: }; protected: - /// Pick a safe ordering and emit instructions for each target node in the - /// graph. - void ScheduleAndEmitDAG(SelectionDAG &DAG); - /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated /// by tblgen. Others should not call it. void SelectInlineAsmMemoryOperands(std::vector &Ops, @@ -187,6 +185,10 @@ private: void ComputeLiveOutVRegInfo(SelectionDAG &DAG); + /// Pick a safe ordering and emit instructions for each target node in the + /// graph. + void ScheduleAndEmitDAG(SelectionDAG &DAG); + /// SwitchCases - Vector of CaseBlock structures used to communicate /// SwitchInst code generation information. std::vector SwitchCases; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 1124f37d2e8..8cfc334c025 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -43,9 +43,10 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/Timer.h" #include using namespace llvm; @@ -5354,7 +5355,14 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Third, instruction select all of the operations to machine code, adding the // code to the MachineBasicBlock. - InstructionSelectBasicBlock(DAG); + InstructionSelect(DAG); + + // Emit machine code to BB. This can change 'BB' to the last block being + // inserted into. + ScheduleAndEmitDAG(DAG); + + // Perform target specific isel post processing. + InstructionSelectPostProcessing(DAG); DOUT << "Selected machine code:\n"; DEBUG(BB->dump()); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index eaa16fc9d68..34f6cb923d5 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -54,7 +54,7 @@ public: } SDNode *Select(SDOperand Op); - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset, SDOperand &Opc); bool SelectAddrMode2Offset(SDOperand Op, SDOperand N, @@ -91,13 +91,11 @@ public: }; } -void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - ScheduleAndEmitDAG(DAG); } bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N, diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index c7eefccd409..5275f7c5a21 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -161,9 +161,9 @@ namespace { // target-specific node if it hasn't already been changed. SDNode *Select(SDOperand Op); - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); virtual const char *getPassName() const { return "Alpha DAG->DAG Pattern Instruction Selection"; @@ -230,17 +230,14 @@ SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { RA, MVT::i64); } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } // Select - Convert the specified operand from a target-independent to a diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index d0261fd5a7d..6bc69ee2181 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -317,9 +317,9 @@ public: return false; } - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); virtual const char *getPassName() const { return "Cell SPU DAG->DAG Pattern Instruction Selection"; @@ -339,19 +339,16 @@ public: } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. void -SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) +SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } /*! diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 0a80653b6f3..dcd1fe2fcc7 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -78,9 +78,9 @@ namespace { /// operation. bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); virtual const char *getPassName() const { return "IA64 (Itanium) DAG->DAG Instruction Selector"; @@ -94,17 +94,14 @@ private: }; } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) { diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 283d69373a7..0c967e2e8ab 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -66,7 +66,7 @@ public: SelectionDAGISel(MipsLowering), TM(tm), MipsLowering(*TM.getTargetLowering()) {} - virtual void InstructionSelectBasicBlock(SelectionDAG &SD); + virtual void InstructionSelect(SelectionDAG &SD); // Pass Name virtual const char *getPassName() const { @@ -100,10 +100,10 @@ private: } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. void MipsDAGToDAGISel:: -InstructionSelectBasicBlock(SelectionDAG &SD) +InstructionSelect(SelectionDAG &SD) { DEBUG(BB->dump()); // Codegen the basic block. @@ -120,9 +120,6 @@ InstructionSelectBasicBlock(SelectionDAG &SD) #endif SD.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(SD); } /// getGlobalBaseReg - Output the instructions required to put the diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp index 512893b2e6a..325e71e7bcf 100644 --- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp +++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp @@ -61,7 +61,7 @@ public: SelectionDAGISel(PIC16Lowering), TM(tm), PIC16Lowering(*TM.getTargetLowering()) {} - virtual void InstructionSelectBasicBlock(SelectionDAG &SD); + virtual void InstructionSelect(SelectionDAG &SD); // Pass Name virtual const char *getPassName() const { @@ -97,9 +97,9 @@ private: } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD) +void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD) { DEBUG(BB->dump()); // Codegen the basic block. @@ -115,9 +115,6 @@ void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD) DOUT << "===== Instruction selection ends:\n"; SD.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(SD); } diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 45a0831fdff..1dea2eec4b9 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -173,9 +173,9 @@ namespace { SDOperand BuildSDIVSequence(SDNode *N); SDOperand BuildUDIVSequence(SDNode *N); - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); void InsertVRSaveCode(Function &Fn); @@ -201,17 +201,14 @@ private: }; } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void PPCDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } /// InsertVRSaveCode - Once the entire function has been instruction selected, diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 3ef27dd642b..50690ca300f 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -47,9 +47,9 @@ public: bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset); - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); virtual const char *getPassName() const { return "SPARC DAG->DAG Pattern Instruction Selection"; @@ -60,17 +60,14 @@ public: }; } // end anonymous namespace -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 3a4496f0025..895c2cf5140 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -32,7 +32,6 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" @@ -111,6 +110,10 @@ namespace { /// base register. unsigned GlobalBaseReg; + /// CurBB - Current BB being isel'd. + /// + MachineBasicBlock *CurBB; + public: X86DAGToDAGISel(X86TargetMachine &tm, bool fast) : SelectionDAGISel(X86Lowering), @@ -128,9 +131,13 @@ namespace { return "X86 DAG->DAG Instruction Selection"; } - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); + + /// InstructionSelectPostProcessing - Post processing of selected and + /// scheduled basic blocks. + virtual void InstructionSelectPostProcessing(SelectionDAG &DAG); virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); @@ -554,10 +561,10 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) { /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel /// when it has created a SelectionDAG for us to codegen. -void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { - DEBUG(BB->dump()); - MachineFunction::iterator FirstMBB = BB; +void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { + CurBB = BB; // BB can change as result of isel. + DEBUG(BB->dump()); if (!FastISel) PreprocessForRMW(DAG); @@ -575,11 +582,9 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { #endif DAG.RemoveDeadNodes(); +} - // Emit machine code to BB. This can change 'BB' to the last block being - // inserted into. - ScheduleAndEmitDAG(DAG); - +void X86DAGToDAGISel::InstructionSelectPostProcessing(SelectionDAG &DAG) { // If we are emitting FP stack code, scan the basic block to determine if this // block defines any FP values. If so, put an FP_REG_KILL instruction before // the terminator of the block. @@ -592,7 +597,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { // Scan all of the machine instructions in these MBBs, checking for FP // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.) - MachineFunction::iterator MBBI = FirstMBB; + MachineFunction::iterator MBBI = CurBB; MachineFunction::iterator EndMBB = BB; ++EndMBB; for (; MBBI != EndMBB; ++MBBI) { MachineBasicBlock *MBB = MBBI;