From 423aae30b2a606d5129e008b88384eca38cd9818 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 15 Sep 2011 22:34:29 +0000 Subject: [PATCH] Thumb2 assembly parsing and encoding for SHASX/SHSAX. llvm-svn: 139870 --- lib/Target/ARM/ARMInstrInfo.td | 4 +++ test/MC/ARM/basic-thumb2-instructions.s | 36 +++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 72793e0e333..c5e4b8653c0 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4946,6 +4946,10 @@ def : MnemonicAlias<"srs", "srsia">; def : MnemonicAlias<"qsubaddx", "qsax">; // SASX == SADDSUBX def : MnemonicAlias<"saddsubx", "sasx">; +// SHASX == SHADDSUBX +def : MnemonicAlias<"shaddsubx", "shasx">; +// SHSAX == SHSUBADDX +def : MnemonicAlias<"shsubaddx", "shsax">; // LDRSBT/LDRHT/LDRSHT post-index offset if optional. // Note that the write-back output register is a dummy operand for MC (it's diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 718189cad4e..466bebf6d75 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -1678,6 +1678,42 @@ _func: @ CHECK: seveq.w @ encoding: [0xaf,0xf3,0x04,0x80] +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shasx r4, r8, r2 + it gt + shasxgt r4, r8, r2 + shaddsubx r4, r8, r2 + it gt + shaddsubxgt r4, r8, r2 + +@ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shsax r4, r8, r2 + it gt + shsaxgt r4, r8, r2 + shsubaddx r4, r8, r2 + it gt + shsubaddxgt r4, r8, r2 + +@ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shsaxgt r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shsaxgt r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] + + @------------------------------------------------------------------------------ @ SUB (register) @------------------------------------------------------------------------------