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Add operand encoding for Thumb2 addw SP + imm. rdar://8745434

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llvm-svn: 121305
This commit is contained in:
Jim Grosbach 2010-12-08 22:50:19 +00:00
parent e1eb84a44a
commit 51082ed2a4
1 changed files with 8 additions and 4 deletions
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12
lib/Target/ARM/ARMInstrThumb2.td
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@ -1152,14 +1152,18 @@ def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
let Inst{19-16} = 0b1101; // Rn = sp let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0; let Inst{15} = 0;
} }
def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm), def t2ADDrSPi12 : T2I<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> { IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
bits<4> Rd;
bits<12> imm;
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{26} = imm{11};
let Inst{24-21} = 0b0000; let Inst{25-20} = 0b100000;
let Inst{20} = 0; // The S bit.
let Inst{19-16} = 0b1101; // Rn = sp let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0; let Inst{15} = 0;
let Inst{14-12} = imm{10-8};
let Inst{11-8} = Rd;
let Inst{7-0} = imm{7-0};
} }
// ADD r, sp, so_reg // ADD r, sp, so_reg