diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 18da8168a94..41ba14205da 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3159,6 +3159,28 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
     break;
   }
+  case ISD::ConstantVec: {
+    unsigned NumElements = Node->getNumOperands();
+    // If we only have two elements left in the constant vector, just break it
+    // apart into the two scalar constants it contains.  Otherwise, bisect the
+    // ConstantVec, and return each half as a new ConstantVec.
+    // FIXME: this is hard coded as big endian, it may have to change to support
+    // SSE and Alpha MVI
+    if (NumElements == 2) {
+      Hi = Node->getOperand(0);
+      Lo = Node->getOperand(1);
+    } else {
+      NumElements /= 2; 
+      std::vector<SDOperand> LoOps, HiOps;
+      for (unsigned I = 0, E = NumElements; I < E; ++I) {
+        HiOps.push_back(Node->getOperand(I));
+        LoOps.push_back(Node->getOperand(I+NumElements));
+      }
+      Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
+      Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
+    }
+    break;
+  }
 
   case ISD::BUILD_PAIR:
     // Legalize both operands.  FIXME: in the future we should handle the case
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 97597e053f4..c6cc60ac0c4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -318,9 +318,15 @@ public:
         }
         // Handle the case where we have a 1-element vector, in which
         // case we want to immediately turn it into a scalar constant.
-        if (Ops.size() == 1)
+        if (Ops.size() == 1) {
           return N = Ops[0];
-        return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
+        } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+          return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
+        } else {
+          // If the packed type isn't legal, then create a ConstantVec node with
+          // generic Vector type instead.
+          return N = DAG.getNode(ISD::ConstantVec, MVT::Vector, Ops);
+        }
       } else {
         // Canonicalize all constant ints to be unsigned.
         return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);