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[SystemZ] Add floating-point test data class instructions.

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These are not used by CodeGen yet - ISD combiners creating the new node
will come in subsequent patches.

llvm-svn: 274108
This commit is contained in:
Marcin Koscielnicki 2016-06-29 07:29:07 +00:00
parent c1b761b81b
commit 5a2ffabc1e
8 changed files with 164 additions and 0 deletions
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1
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -4684,6 +4684,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
OPCODE(ATOMIC_CMP_SWAPW);
OPCODE(LRV);
OPCODE(STRV);
OPCODE(TDC);
OPCODE(PREFETCH);
}
return nullptr;

6
lib/Target/SystemZ/SystemZISelLowering.h
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@ -324,6 +324,12 @@ enum NodeType : unsigned {
// Operand 2: the type of store (i16, i32, i64)
STRV,
// Test Data Class.
//
// Operand 0: the value to test
// Operand 1: the bit mask
TDC,
// Prefetch from the second operand using the 4-bit control code in
// the first operand. The code is 1 for a load prefetch and 2 for
// a store prefetch.

7
lib/Target/SystemZ/SystemZInstrFP.td
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@ -447,6 +447,13 @@ let Defs = [CC], CCValues = 0xF in {
def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
}
// Test Data Class.
let Defs = [CC], CCValues = 0xC in {
def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>;
def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>;
def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
}
//===----------------------------------------------------------------------===//
// Peepholes
//===----------------------------------------------------------------------===//

12
lib/Target/SystemZ/SystemZInstrFormats.td
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@ -1001,6 +1001,10 @@ class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
// Compare:
// Two input operands and an implicit CC output operand.
//
// Test:
// Two input operands and an implicit CC output operand. The second
// input operand is an "address" operand used as a test class mask.
//
// Ternary:
// One register output operand and three input operands.
//
@ -1956,6 +1960,14 @@ class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let M5 = 0;
}
class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls>
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, bdxaddr12only:$XBD2)]> {
let M3 = 0;
}
class TernaryRRD<string mnemonic, bits<16> opcode,
SDPatternOperator operator, RegisterOperand cls>
: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),

3
lib/Target/SystemZ/SystemZOperators.td
View File

@ -145,6 +145,7 @@ def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisVT<4, i32>]>;
def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>;
//===----------------------------------------------------------------------===//
// Node definitions
@ -204,6 +205,8 @@ def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap,
def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>;
// Defined because the index is an i32 rather than a pointer.
def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDT_ZInsertVectorElt>;

63
test/MC/Disassembler/SystemZ/insns.txt
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@ -9040,6 +9040,69 @@
# CHECK: tbeginc 4095(%r15), 42
0xe5 0x61 0xff 0xff 0x00 0x2a
# CHECK: tcdb %f0, 0
0xed 0x00 0x00 0x00 0x00 0x11
# CHECK: tcdb %f0, 4095
0xed 0x00 0x0f 0xff 0x00 0x11
# CHECK: tcdb %f0, 0(%r1)
0xed 0x00 0x10 0x00 0x00 0x11
# CHECK: tcdb %f0, 0(%r15)
0xed 0x00 0xf0 0x00 0x00 0x11
# CHECK: tcdb %f0, 4095(%r1,%r15)
0xed 0x01 0xff 0xff 0x00 0x11
# CHECK: tcdb %f0, 4095(%r15,%r1)
0xed 0x0f 0x1f 0xff 0x00 0x11
# CHECK: tcdb %f15, 0
0xed 0xf0 0x00 0x00 0x00 0x11
# CHECK: tceb %f0, 0
0xed 0x00 0x00 0x00 0x00 0x10
# CHECK: tceb %f0, 4095
0xed 0x00 0x0f 0xff 0x00 0x10
# CHECK: tceb %f0, 0(%r1)
0xed 0x00 0x10 0x00 0x00 0x10
# CHECK: tceb %f0, 0(%r15)
0xed 0x00 0xf0 0x00 0x00 0x10
# CHECK: tceb %f0, 4095(%r1,%r15)
0xed 0x01 0xff 0xff 0x00 0x10
# CHECK: tceb %f0, 4095(%r15,%r1)
0xed 0x0f 0x1f 0xff 0x00 0x10
# CHECK: tceb %f15, 0
0xed 0xf0 0x00 0x00 0x00 0x10
# CHECK: tcxb %f0, 0
0xed 0x00 0x00 0x00 0x00 0x12
# CHECK: tcxb %f0, 4095
0xed 0x00 0x0f 0xff 0x00 0x12
# CHECK: tcxb %f0, 0(%r1)
0xed 0x00 0x10 0x00 0x00 0x12
# CHECK: tcxb %f0, 0(%r15)
0xed 0x00 0xf0 0x00 0x00 0x12
# CHECK: tcxb %f0, 4095(%r1,%r15)
0xed 0x01 0xff 0xff 0x00 0x12
# CHECK: tcxb %f0, 4095(%r15,%r1)
0xed 0x0f 0x1f 0xff 0x00 0x12
# CHECK: tcxb %f13, 0
0xed 0xd0 0x00 0x00 0x00 0x12
# CHECK: tend
0xb2 0xf8 0x00 0x00

24
test/MC/SystemZ/insn-bad.s
View File

@ -3328,6 +3328,30 @@
sy %r0, -524289
sy %r0, 524288
#CHECK: error: invalid operand
#CHECK: tcdb %f0, -1
#CHECK: error: invalid operand
#CHECK: tcdb %f0, 4096
tcdb %f0, -1
tcdb %f0, 4096
#CHECK: error: invalid operand
#CHECK: tceb %f0, -1
#CHECK: error: invalid operand
#CHECK: tceb %f0, 4096
tceb %f0, -1
tceb %f0, 4096
#CHECK: error: invalid operand
#CHECK: tcxb %f0, -1
#CHECK: error: invalid operand
#CHECK: tcxb %f0, 4096
tcxb %f0, -1
tcxb %f0, 4096
#CHECK: error: invalid operand
#CHECK: tm -1, 0
#CHECK: error: invalid operand

48
test/MC/SystemZ/insn-good.s
View File

@ -9289,6 +9289,54 @@
sy %r0, 524287(%r15,%r1)
sy %r15, 0
#CHECK: tcdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x11]
#CHECK: tcdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x11]
#CHECK: tcdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x11]
#CHECK: tcdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x11]
#CHECK: tcdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x11]
#CHECK: tcdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x11]
#CHECK: tcdb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x11]
tcdb %f0, 0
tcdb %f0, 4095
tcdb %f0, 0(%r1)
tcdb %f0, 0(%r15)
tcdb %f0, 4095(%r1,%r15)
tcdb %f0, 4095(%r15,%r1)
tcdb %f15, 0
#CHECK: tceb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x10]
#CHECK: tceb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x10]
#CHECK: tceb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x10]
#CHECK: tceb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x10]
#CHECK: tceb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x10]
#CHECK: tceb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x10]
#CHECK: tceb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x10]
tceb %f0, 0
tceb %f0, 4095
tceb %f0, 0(%r1)
tceb %f0, 0(%r15)
tceb %f0, 4095(%r1,%r15)
tceb %f0, 4095(%r15,%r1)
tceb %f15, 0
#CHECK: tcxb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x12]
#CHECK: tcxb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x12]
#CHECK: tcxb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x12]
#CHECK: tcxb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x12]
#CHECK: tcxb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x12]
#CHECK: tcxb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x12]
#CHECK: tcxb %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x12]
tcxb %f0, 0
tcxb %f0, 4095
tcxb %f0, 0(%r1)
tcxb %f0, 0(%r15)
tcxb %f0, 4095(%r1,%r15)
tcxb %f0, 4095(%r15,%r1)
tcxb %f13, 0
#CHECK: tm 0, 0 # encoding: [0x91,0x00,0x00,0x00]
#CHECK: tm 4095, 0 # encoding: [0x91,0x00,0x0f,0xff]
#CHECK: tm 0, 255 # encoding: [0x91,0xff,0x00,0x00]