From 5de40afc431f2fbdc41d00c4c5bf298c41e24600 Mon Sep 17 00:00:00 2001
From: Nate Begeman <natebegeman@mac.com>
Date: Thu, 1 Dec 2005 04:48:26 +0000
Subject: [PATCH] Cosmetic change, better reflects actual values

llvm-svn: 24562
---
 lib/Target/PowerPC/PPCRegisterInfo.td | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index c4ec815c17b..d62045d8103 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -28,8 +28,8 @@ class GP8<GPR Alias> : PPCReg<Alias.Name> {
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<5> num, string n> : PPCReg<n> {
-  field bits<5> Num = num;
+class SPR<bits<10> num, string n> : PPCReg<n> {
+  field bits<10> Num = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
@@ -126,12 +126,11 @@ def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">;
 def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;
 
 // Link register
-// FIXME: encode actual spr numbers here
-def LR  : SPR<2,   "lr">;
+def LR  : SPR<8, "lr">;
 // Count register
-def CTR : SPR<3, "ctr">;
+def CTR : SPR<9, "ctr">;
 // VRsave register
-def VRSAVE: SPR<4, "VRsave">;
+def VRSAVE: SPR<256, "VRsave">;
 
 /// Register classes
 // Allocate volatiles first