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[MachineVerifier] Check that even generic vregs comply to regclass constraints.

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We used to not check generic vregs, but that is actually a mistake given
nothing in the GlobalISel pipeline is going to fix the constraints on
target specific instructions. Therefore, the target has to have them
right from the start.

llvm-svn: 290380
This commit is contained in:
Quentin Colombet 2016-12-22 21:56:39 +00:00
parent 3a3a5a1c0d
commit 6877ce89ac
1 changed files with 15 additions and 0 deletions
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15
lib/CodeGen/MachineVerifier.cpp
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@ -1056,6 +1056,21 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
MONum);
return;
}
// If this is a target specific instruction and this operand
// has register class constraint, the virtual register must
// comply to it.
if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
TII->getRegClass(MCID, MONum, TRI, *MF)) {
report("Virtual register does not match instruction constraint", MO,
MONum);
errs() << "Expect register class "
<< TRI->getRegClassName(
TII->getRegClass(MCID, MONum, TRI, *MF))
<< " but got nothing\n";
return;
}
break;
}
if (SubIdx) {