From 6877ce89ac2ef25a689a2383757b7ac7e1609aa4 Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Thu, 22 Dec 2016 21:56:39 +0000
Subject: [PATCH] [MachineVerifier] Check that even generic vregs comply to
 regclass constraints.

We used to not check generic vregs, but that is actually a mistake given
nothing in the GlobalISel pipeline is going to fix the constraints on
target specific instructions. Therefore, the target has to have them
right from the start.

llvm-svn: 290380
---
 lib/CodeGen/MachineVerifier.cpp | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index c790fc3cbf6..7eb42ecdf0a 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -1056,6 +1056,21 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
                    MONum);
             return;
           }
+
+          // If this is a target specific instruction and this operand
+          // has register class constraint, the virtual register must
+          // comply to it.
+          if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
+              TII->getRegClass(MCID, MONum, TRI, *MF)) {
+            report("Virtual register does not match instruction constraint", MO,
+                   MONum);
+            errs() << "Expect register class "
+                   << TRI->getRegClassName(
+                          TII->getRegClass(MCID, MONum, TRI, *MF))
+                   << " but got nothing\n";
+            return;
+          }
+
           break;
         }
         if (SubIdx) {