diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index e5cddada583..d775d8278f2 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -385,7 +385,7 @@ public:
   /// getPostIndexedAddressParts - returns true by value, base pointer and
   /// offset pointer and addressing mode by reference if this node can be
   /// combined with a load / store to form a post-indexed load / store.
-  virtual bool getPostIndexedAddressParts(SDNode *N, MVT::ValueType VT,
+  virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                           SDOperand &Base, SDOperand &Offset,
                                           ISD::MemOpAddrMode &AM,
                                           SelectionDAG &DAG) {
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 430cf5c6f56..d211077b90d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -282,10 +282,8 @@ namespace {
       MVT::ValueType VT;
       if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
         Ptr = LD->getBasePtr();
-        VT  = LD->getLoadedVT();
       } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
         Ptr = ST->getBasePtr();
-        VT  = ST->getStoredVT();
         isLoad = false;
       } else
         return false;
@@ -301,7 +299,7 @@ namespace {
           SDOperand BasePtr;
           SDOperand Offset;
           ISD::MemOpAddrMode AM = ISD::UNINDEXED;
-          if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG)) {
+          if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
             if (Ptr == Offset)
               std::swap(BasePtr, Offset);
             if (Ptr != BasePtr)