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[XCore] Don't create invalid MKMSK instructions inside loadImmediate().
Summary: Previously loadImmediate() would produce MKMSK instructions with invalid immediate values such as mkmsk r0, 9. Fix this by checking the mask size is valid. Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3289 llvm-svn: 206163
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@ -428,13 +428,21 @@ static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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return val < (1 << 16);
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}
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}
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static bool isImmMskBitp(unsigned val) {
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if (!isMask_32(val)) {
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return false;
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}
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int N = Log2_32(val) + 1;
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return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
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}
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MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
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MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
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MachineBasicBlock &MBB,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MachineBasicBlock::iterator MI,
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unsigned Reg, uint64_t Value) const {
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unsigned Reg, uint64_t Value) const {
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DebugLoc dl;
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DebugLoc dl;
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if (MI != MBB.end()) dl = MI->getDebugLoc();
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if (MI != MBB.end()) dl = MI->getDebugLoc();
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if (isMask_32(Value)) {
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if (isImmMskBitp(Value)) {
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int N = Log2_32(Value) + 1;
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int N = Log2_32(Value) + 1;
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return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
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return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
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}
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}
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@ -206,14 +206,41 @@ entry:
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ret i32 %i
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ret i32 %i
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}
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}
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; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
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; CHECKFP-LABEL:f8
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; CHECKFP: entsp 258
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: mkmsk [[REG:r[0-9]+]], 8
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; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}}
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 258
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;
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
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; CHECK-LABEL:f8
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; CHECK: entsp 257
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; CHECK-NEXT: ldaw r0, sp[254]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: retsp 257
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define void @f8() nounwind {
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entry:
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%0 = alloca [256 x i32]
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%1 = getelementptr inbounds [256 x i32]* %0, i32 0, i32 253
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call void @f5(i32* %1)
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ret void
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}
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; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
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; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
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; CHECKFP-LABEL:f8
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; CHECKFP-LABEL:f9
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; CHECKFP: entsp 32770
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; CHECKFP: entsp 32770
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: mkmsk r1, 15
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; CHECKFP-NEXT: ldc [[REG:r[0-9]+]], 32767
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; CHECKFP-NEXT: ldaw r0, r10[r1]
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; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}}
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: ldaw sp, sp[1]
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@ -222,12 +249,12 @@ entry:
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; CHECKFP-NEXT: retsp 32770
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; CHECKFP-NEXT: retsp 32770
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;
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;
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768
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; CHECK-LABEL:f8
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; CHECK-LABEL:f9
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; CHECK: entsp 32771
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; CHECK: entsp 32771
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; CHECK-NEXT: ldaw r0, sp[32768]
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; CHECK-NEXT: ldaw r0, sp[32768]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: retsp 32771
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; CHECK-NEXT: retsp 32771
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define void @f8() nounwind {
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define void @f9() nounwind {
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entry:
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entry:
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%0 = alloca [32768 x i32]
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%0 = alloca [32768 x i32]
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%1 = getelementptr inbounds [32768 x i32]* %0, i32 0, i32 32765
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%1 = getelementptr inbounds [32768 x i32]* %0, i32 0, i32 32765
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