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[AVR] Fix bug which caused assertion errors for some FRMIDX instructions

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Previously, if a basic block ended with a FRMIDX instruction, we would
end up doing something like this.

*std::next(MBB.end())

Which would hit an error:

"Assertion `!NodePtr->isKnownSentinel()' failed."

llvm-svn: 307057
This commit is contained in:
Dylan McKay 2017-07-04 04:40:06 +00:00
parent e74f1e970e
commit 71adee46e4
2 changed files with 41 additions and 3 deletions
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11
lib/Target/AVR/AVRRegisterInfo.cpp
View File

@ -95,7 +95,8 @@ AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
} }
/// Fold a frame offset shared between two add instructions into a single one. /// Fold a frame offset shared between two add instructions into a single one.
static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) { static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, unsigned DstReg) {
MachineInstr &MI = *II;
int Opcode = MI.getOpcode(); int Opcode = MI.getOpcode();
// Don't bother trying if the next instruction is not an add or a sub. // Don't bother trying if the next instruction is not an add or a sub.
@ -120,6 +121,7 @@ static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
} }
// Finally remove the instruction. // Finally remove the instruction.
II++;
MI.eraseFromParent(); MI.eraseFromParent();
} }
@ -158,6 +160,8 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned DstReg = MI.getOperand(0).getReg(); unsigned DstReg = MI.getOperand(0).getReg();
assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
II++; // Skip over the FRMIDX (and now MOVW) instruction.
// Generally, to load a frame address two add instructions are emitted that // Generally, to load a frame address two add instructions are emitted that
// could get folded into a single one: // could get folded into a single one:
// movw r31:r30, r29:r28 // movw r31:r30, r29:r28
@ -166,7 +170,8 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// to: // to:
// movw r31:r30, r29:r28 // movw r31:r30, r29:r28
// adiw r31:r30, 45 // adiw r31:r30, 45
foldFrameOffset(*std::next(II), Offset, DstReg); if (II != MBB.end())
foldFrameOffset(II, Offset, DstReg);
// Select the best opcode based on DstReg and the offset size. // Select the best opcode based on DstReg and the offset size.
switch (DstReg) { switch (DstReg) {
@ -187,7 +192,7 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} }
} }
MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg) MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
.addReg(DstReg, RegState::Kill) .addReg(DstReg, RegState::Kill)
.addImm(Offset); .addImm(Offset);
New->getOperand(3).setIsDead(); New->getOperand(3).setIsDead();

33
test/CodeGen/AVR/frmidx-iterator-bug.ll Normal file
View File

@ -0,0 +1,33 @@
; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
%str_slice = type { i8*, i16 }
%Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
; CHECK-LABEL: step
define void @step(%Machine*) {
ret void
}
; CHECK-LABEL: main
define void @main() {
start:
%machine = alloca %Machine, align 8
%v0 = bitcast %Machine* %machine to i8*
%v1 = getelementptr inbounds %Machine, %Machine* %machine, i16 0, i32 2
%v2 = load i16, i16* %v1, align 2
br label %bb2.i5
bb2.i5:
%v18 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
%v19 = icmp sgt i8 %v18, -1
br i1 %v19, label %bb2.i5, label %bb.exit6
bb.exit6:
%v20 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
br label %bb7
bb7:
call void @step(%Machine* %machine)
br label %bb7
}