From 72a03073f61478c4c09539d7da37e18ea6fadf94 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 18 Mar 2019 22:06:14 +0000 Subject: [PATCH] [X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode. llvm-svn: 356419 --- lib/Target/X86/X86InstrExtension.td | 4 ++-- test/MC/X86/x86_errors.s | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td index 0b06b3e58fd..06e605fe5db 100644 --- a/lib/Target/X86/X86InstrExtension.td +++ b/lib/Target/X86/X86InstrExtension.td @@ -28,11 +28,11 @@ let hasSideEffects = 0 in { let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX) def CDQE : RI<0x98, RawFrm, (outs), (ins), - "{cltq|cdqe}", []>, Sched<[WriteALU]>; + "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>; let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX) def CQO : RI<0x99, RawFrm, (outs), (ins), - "{cqto|cqo}", []>, Sched<[WriteALU]>; + "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>; } // Sign/Zero extenders diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s index d9995918389..273abd57fba 100644 --- a/test/MC/X86/x86_errors.s +++ b/test/MC/X86/x86_errors.s @@ -158,3 +158,9 @@ mov v_ecx(%eax), %ecx // 32: 7: error: invalid operand for instruction // 64: 7: error: invalid operand for instruction addb (%dx), %al + +// 32: error: instruction requires: 64-bit mode +cqto + +// 32: error: instruction requires: 64-bit mode +cltq