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AArch64: disallow "fmov sD, #-0.0" during assembly.

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We weren't checking the sign of the floating point immediate before translating
it to "fmov sD, wzr". Similarly for D-regs.

Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's
not a blessed alias (and I don't think it should be since people expect writing
sD to zero out the high lanes, and there's no dD equivalent). So an error it is.

rdar://20455398

llvm-svn: 234372
This commit is contained in:
Tim Northover 2015-04-07 22:49:47 +00:00
parent 212b8006f8
commit 75657ea420
2 changed files with 12 additions and 3 deletions
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7
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -2090,15 +2090,16 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
const AsmToken &Tok = Parser.getTok();
if (Tok.is(AsmToken::Real)) {
APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
if (isNegative)
RealVal.changeSign();
uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
// If we had a '-' in front, toggle the sign bit.
IntVal ^= (uint64_t)isNegative << 63;
int Val = AArch64_AM::getFP64Imm(APInt(64, IntVal));
Parser.Lex(); // Eat the token.
// Check for out of range values. As an exception, we let Zero through,
// as we handle that special case in post-processing before matching in
// order to use the zero register for it.
if (Val == -1 && !RealVal.isZero()) {
if (Val == -1 && !RealVal.isPosZero()) {
TokError("expected compatible register or floating-point constant");
return MatchOperand_ParseFail;
}

8
test/MC/AArch64/arm64-fp-encoding-error.s Normal file
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@ -0,0 +1,8 @@
; RUN: not llvm-mc -triple arm64-apple-ios8.0 %s -o /dev/null 2>&1 | FileCheck %s
fmov s0, #-0.0
; CHECK: error: expected compatible register or floating-point constant
fmov d0, #-0.0
; CHECK: error: expected compatible register or floating-point constant