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MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
before encoding. llvm-svn: 104707
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6f08a37562
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@ -112,10 +112,7 @@ public:
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/// relaxation.
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///
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/// \arg Inst - The instruction to test.
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/// \arg Fixups - The actual fixups this instruction encoded to, for potential
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/// use by the target backend.
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virtual bool MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCFixup> &Fixups) const = 0;
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virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;
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/// RelaxInstruction - Relax the instruction in the given fragment to the next
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/// wider instruction.
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@ -787,7 +787,7 @@ bool MCAssembler::FragmentNeedsRelaxation(const MCInstFragment *IF,
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// If this inst doesn't ever need relaxation, ignore it. This occurs when we
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// are intentionally pushing out inst fragments, or because we relaxed a
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// previous instruction to one that doesn't need relaxation.
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if (!getBackend().MayNeedRelaxation(IF->getInst(), IF->getFixups()))
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if (!getBackend().MayNeedRelaxation(IF->getInst()))
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return false;
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for (MCInstFragment::const_fixup_iterator it = IF->fixup_begin(),
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@ -452,7 +452,7 @@ void MCMachOStreamer::EmitInstruction(const MCInst &Inst) {
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// total knowledge about undefined symbols at that point). Even now, though,
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// we can do a decent job, especially on Darwin where scattering means that we
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// are going to often know that we can never fully resolve a fixup.
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if (Assembler.getBackend().MayNeedRelaxation(Inst, AsmFixups)) {
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if (Assembler.getBackend().MayNeedRelaxation(Inst)) {
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MCInstFragment *IF = new MCInstFragment(Inst, CurSectionData);
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IF->setAtom(CurrentAtomMap.lookup(CurSectionData));
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@ -54,8 +54,7 @@ public:
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DF.getContents()[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
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}
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bool MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCFixup> &Fixups) const;
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bool MayNeedRelaxation(const MCInst &Inst) const;
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void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
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@ -88,31 +87,16 @@ static unsigned getRelaxedOpcode(unsigned Op) {
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}
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}
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCFixup> &Fixups) const {
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for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
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const MCFixup &F = Fixups[i];
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
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// Check if this instruction is ever relaxable.
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if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
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return false;
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// We don't support relaxing anything else currently. Make sure we error out
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// if we see a non-constant 1 or 2 byte fixup.
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//
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// FIXME: We should need to check this here, this is better checked in the
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// object writer which should be verifying that any final relocations match
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// the expected fixup. However, that code is more complicated and hasn't
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// been written yet. See the FIXMEs in MachObjectWriter.cpp.
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if ((F.getKind() == FK_Data_1 || F.getKind() == FK_Data_2) &&
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!isa<MCConstantExpr>(F.getValue()))
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report_fatal_error("unexpected small fixup with a non-constant operand!");
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// Check for a 1byte pcrel fixup, and enforce that we would know how to
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// relax this instruction.
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if (unsigned(F.getKind()) == X86::reloc_pcrel_1byte) {
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assert(getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode());
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return true;
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}
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}
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return false;
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// If so, just assume it can be relaxed. Once we support relaxing more complex
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// instructions we should check that the instruction actually has symbolic
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// operands before doing this, but we need to be careful about things like
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// PCrel.
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return true;
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}
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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