diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 26a02babd2c..258d807f701 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -736,7 +736,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
 static
 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
-                            TargetLowering &TLI) {
+                            const TargetLowering &TLI) {
   int SVOffset = LD->getSrcValueOffset();
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 34f33b0bccc..b83d537e372 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4982,7 +4982,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
       return "<<Unknown Machine Node>>";
     }
     if (G) {
-      TargetLowering &TLI = G->getTargetLoweringInfo();
+      const TargetLowering &TLI = G->getTargetLoweringInfo();
       const char *Name = TLI.getTargetNodeName(getOpcode());
       if (Name) return Name;
       return "<<Unknown Target Node>>";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 5740cc93453..60a4f61d256 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -380,7 +380,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
                                   MVT ValueVT,
                                   ISD::NodeType AssertOp = ISD::DELETED_NODE) {
   assert(NumParts > 0 && "No parts to assemble!");
-  TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue Val = Parts[0];
 
   if (NumParts > 1) {
@@ -525,7 +525,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
 static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
                            SDValue *Parts, unsigned NumParts, MVT PartVT,
                            ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
-  TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   MVT PtrVT = TLI.getPointerTy();
   MVT ValueVT = Val.getValueType();
   unsigned PartBits = PartVT.getSizeInBits();
@@ -648,8 +648,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
   // Handle a multi-element vector.
   MVT IntermediateVT, RegisterVT;
   unsigned NumIntermediates;
-  unsigned NumRegs =
-    DAG.getTargetLoweringInfo()
+  unsigned NumRegs = TLI
       .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
                               RegisterVT);
   unsigned NumElements = ValueVT.getVectorNumElements();
@@ -4819,7 +4818,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
 /// processed uses a memory 'm' constraint.
 static bool
 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
-                          TargetLowering &TLI) {
+                          const TargetLowering &TLI) {
   for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
     InlineAsm::ConstraintInfo &CI = CInfos[i];
     for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 3688a13034d..744ea00acea 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -141,8 +141,8 @@ namespace llvm {
                                       const TargetMachine *TM,
                                       MachineBasicBlock *BB,
                                       bool Fast) {
-    TargetLowering &TLI = IS->getTargetLowering();
-    
+    const TargetLowering &TLI = IS->getTargetLowering();
+
     if (Fast)
       return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
@@ -399,7 +399,7 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
 /// DAG and fixes their tailcall attribute operand.
 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, 
-                                           TargetLowering& TLI) {
+                                           const TargetLowering& TLI) {
   SDNode * Ret = NULL;
   SDValue Terminator = DAG.getRoot();