diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index a8e12d06c0a..3d7a32af6e7 100644
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -163,17 +163,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
     .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
                {S32, S1}, {S64, S1}, {S16, S1}});
 
-  setAction({G_FPTOSI, S32}, Legal);
-  setAction({G_FPTOSI, 1, S32}, Legal);
+  getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
+    .legalFor({{S32, S32}, {S64, S32}});
 
-  setAction({G_SITOFP, S32}, Legal);
-  setAction({G_SITOFP, 1, S32}, Legal);
-
-  setAction({G_UITOFP, S32}, Legal);
-  setAction({G_UITOFP, 1, S32}, Legal);
-
-  setAction({G_FPTOUI, S32}, Legal);
-  setAction({G_FPTOUI, 1, S32}, Legal);
+  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
+    .legalFor({{S32, S32}, {S32, S64}});
 
   setAction({G_FPOW, S32}, Legal);
   setAction({G_FEXP2, S32}, Legal);
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
index d4414bc62f0..60c2e2aecaa 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
@@ -2,13 +2,25 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name: test_fptosi_f32_to_i32
+name: test_fptosi_s32_to_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_fptosi_f32_to_i32
+    ; CHECK-LABEL: name: test_fptosi_s32_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_FPTOSI %0
 ...
+
+---
+name: test_fptosi_s64_to_s32
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_fptosi_s64_to_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_FPTOSI %0
+...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
index aede6af2603..c77b8ed2151 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
@@ -1,14 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name:            test_fptoui
+name: test_fptoui_s32_s32
 body: |
   bb.0:
     liveins: $vgpr0
-    ; CHECK-LABEL: name: test_fptoui
-    ; CHECK: %1:_(s32) = G_FPTOUI %0
 
+    ; CHECK-LABEL: name: test_fptoui_s32_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: $vgpr0 = COPY [[FPTOUI]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_FPTOUI %0
     $vgpr0 = COPY %1
 ...
+
+---
+name: test_fptoui_s32_s64
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: test_fptoui_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: $vgpr0 = COPY [[FPTOUI]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_FPTOUI %0
+    $vgpr0 = COPY %1
+...
+
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
index 649f8903cd1..aa86c5f0253 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
@@ -2,13 +2,32 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 ---
-name: test_sitofp_f32_to_i32
+name: test_sitofp_s32_to_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_sitofp_f32_to_i32
+    ; CHECK-LABEL: name: test_sitofp_s32_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
+    ; CHECK: $vgpr0 = COPY [[SITOFP]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_SITOFP %0
+    $vgpr0 = COPY %1
 ...
+
+---
+name: test_sitofp_s32_to_s64
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_sitofp_s32_to_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s64) = G_SITOFP %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
new file mode 100644
index 00000000000..f376054e646
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_uitofp_s32_to_s32
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_uitofp_s32_to_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
+    ; CHECK: $vgpr0 = COPY [[UITOFP]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_UITOFP %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_uitofp_s32_to_s64
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_uitofp_s32_to_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s64) = G_UITOFP %0
+    $vgpr0_vgpr1 = COPY %1
+...
+