diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index c440caf27a1..7be3cfc0032 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -236,24 +236,6 @@ public: SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4); SDVTList getVTList(const MVT *VTs, unsigned NumVTs); - /// getNodeValueTypes - These are obsolete, use getVTList instead. - const MVT *getNodeValueTypes(MVT VT) { - return getVTList(VT).VTs; - } - const MVT *getNodeValueTypes(MVT VT1, MVT VT2) { - return getVTList(VT1, VT2).VTs; - } - const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3) { - return getVTList(VT1, VT2, VT3).VTs; - } - const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { - return getVTList(VT1, VT2, VT3, VT4).VTs; - } - const MVT *getNodeValueTypes(const std::vector &vtList) { - return getVTList(&vtList[0], (unsigned)vtList.size()).VTs; - } - - //===--------------------------------------------------------------------===// // Node creation methods. // @@ -335,23 +317,23 @@ public: // null) and that there should be a flag result. SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, SDValue Flag) { - const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + SDVTList VTs = getVTList(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; - return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3); } // Similar to last getCopyToReg() except parameter Reg is a SDValue SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N, SDValue Flag) { - const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + SDVTList VTs = getVTList(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Reg, N, Flag }; - return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3); + return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3); } SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) { - const MVT *VTs = getNodeValueTypes(VT, MVT::Other); + SDVTList VTs = getVTList(VT, MVT::Other); SDValue Ops[] = { Chain, getRegister(Reg, VT) }; - return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2); + return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2); } // This version of the getCopyFromReg method takes an extra operand, which @@ -359,9 +341,9 @@ public: // null) and that there should be a flag result. SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT, SDValue Flag) { - const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); + SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag }; - return getNode(ISD::CopyFromReg, dl, VTs, 3, Ops, Flag.getNode() ? 3 : 2); + return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2); } SDValue getCondCode(ISD::CondCode Cond); @@ -383,10 +365,10 @@ public: /// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a /// useful DebugLoc. SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) { - const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + SDVTList VTs = getVTList(MVT::Other, MVT::Flag); SDValue Ops[] = { Chain, Op }; return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(), - VTs, 2, Ops, 2); + VTs, Ops, 2); } /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a2c5396bb93..0ae633c6b53 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -5662,7 +5662,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, SDValue Ops[] = { LHSL, LHSH, Amt }; MVT VT = LHSL.getValueType(); - Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); + Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3); Hi = Lo.getValue(1); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 630a59d8910..66a57dc4320 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1824,7 +1824,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; MVT VT = LHSL.getValueType(); - Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); + Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); Hi = Lo.getValue(1); return; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 3ff0352f668..0f156238985 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2131,7 +2131,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); SDNode *N = NodeAllocator.Allocate(); - new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT)); + new (N) SDNode(Opcode, DL, getVTList(VT)); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); @@ -3724,7 +3724,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps) { - return getNode(Opcode, DL, getNodeValueTypes(ResultTys), ResultTys.size(), + return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), Ops, NumOps); } @@ -4360,82 +4360,75 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); + SDVTList VTs = getVTList(VT1, VT2); SDValue Op; - return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode(); + return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode(); + SDVTList VTs = getVTList(VT1, VT2); + return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); + SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2 }; - return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode(); + return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); + SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2, Op3 }; - return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode(); + return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(VT1, VT2); - return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode(); + SDVTList VTs = getVTList(VT1, VT2); + return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); + SDVTList VTs = getVTList(VT1, VT2, VT3); SDValue Ops[] = { Op1, Op2 }; - return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode(); + return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); + SDVTList VTs = getVTList(VT1, VT2, VT3); SDValue Ops[] = { Op1, Op2, Op3 }; - return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode(); + return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); - return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode(); + SDVTList VTs = getVTList(VT1, VT2, VT3); + return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3, MVT VT4, const SDValue *Ops, unsigned NumOps) { - std::vector VTList; - VTList.push_back(VT1); - VTList.push_back(VT2); - VTList.push_back(VT3); - VTList.push_back(VT4); - const MVT *VTs = getNodeValueTypes(VTList); - return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode(); + SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); + return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, const std::vector &ResultTys, const SDValue *Ops, unsigned NumOps) { - const MVT *VTs = getNodeValueTypes(ResultTys); - return getNode(~Opcode, dl, VTs, ResultTys.size(), - Ops, NumOps).getNode(); + return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); } /// getNodeIfExists - Get the specified node if it's already available, or diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index d46c9c0630e..effb21514a2 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -2825,10 +2825,9 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; - const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), - MVT::Other); + SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), - VTs, 2, Ops, 3); + VTs, Ops, 3); setValue(&I, DSA); DAG.setRoot(DSA.getValue(1)); @@ -2965,7 +2964,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, Ops.push_back(Op); } - std::vector VTs; + std::vector VTArray; if (I.getType() != Type::VoidTy) { MVT VT = TLI.getValueType(I.getType()); if (VT.isVector()) { @@ -2977,36 +2976,32 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, } assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); - VTs.push_back(VT); + VTArray.push_back(VT); } if (HasChain) - VTs.push_back(MVT::Other); + VTArray.push_back(MVT::Other); - const MVT *VTList = DAG.getNodeValueTypes(VTs); + SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size()); // Create the node. SDValue Result; if (IsTgtIntrinsic) { // This is target intrinsic that touches memory Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), - VTList, VTs.size(), - &Ops[0], Ops.size(), + VTs, &Ops[0], Ops.size(), Info.memVT, Info.ptrVal, Info.offset, Info.align, Info.vol, Info.readMem, Info.writeMem); } else if (!HasChain) Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), - VTList, VTs.size(), - &Ops[0], Ops.size()); + VTs, &Ops[0], Ops.size()); else if (I.getType() != Type::VoidTy) Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), - VTList, VTs.size(), - &Ops[0], Ops.size()); + VTs, &Ops[0], Ops.size()); else Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), - VTList, VTs.size(), - &Ops[0], Ops.size()); + VTs, &Ops[0], Ops.size()); if (HasChain) { SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); @@ -3153,11 +3148,8 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { SDValue Op1 = getValue(I.getOperand(1)); SDValue Op2 = getValue(I.getOperand(2)); - MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 }; - SDValue Ops[] = { Op1, Op2 }; - - SDValue Result = DAG.getNode(Op, getCurDebugLoc(), - DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); + SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); + SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2); setValue(&I, Result); return 0; @@ -4211,8 +4203,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::readcyclecounter: { SDValue Op = getRoot(); SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl, - DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, - &Op, 1); + DAG.getVTList(MVT::i64, MVT::Other), + &Op, 1); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); return 0; @@ -4256,7 +4248,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::stacksave: { SDValue Op = getRoot(); SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl, - DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); + DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); return 0; @@ -4304,9 +4296,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Ops[5] = DAG.getSrcValue(F); SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl, - DAG.getNodeValueTypes(TLI.getPointerTy(), - MVT::Other), 2, - Ops, 6); + DAG.getVTList(TLI.getPointerTy(), MVT::Other), + Ops, 6); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); @@ -5393,7 +5384,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { if (Flag.getNode()) AsmNodeOperands.push_back(Flag); Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), - DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, + DAG.getVTList(MVT::Other, MVT::Flag), &AsmNodeOperands[0], AsmNodeOperands.size()); Flag = Chain.getValue(1); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 8489ad249f9..9432e486db2 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -475,16 +475,16 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); if (!Subtarget->hasABICall()) { - const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); + SDVTList VTs = DAG.getVTList(MVT::i32); SDValue Ops[] = { GA }; // %gp_rel relocation if (!isa(GV) && IsGlobalInSmallSection(GV)) { - SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1); + SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, Ops, 1); SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); } // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); @@ -523,9 +523,9 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { - const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); + SDVTList VTs = DAG.getVTList(MVT::i32); SDValue Ops[] = { JTI }; - HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); + HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1); } else // Emit Load from Global Pointer HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6ca4bd8f1e8..ff8382a5abf 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5481,11 +5481,11 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, break; } if (Opcode != 0) { - const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); SmallVector Ops; for (unsigned i = 0; i != NumOperands; ++i) Ops.push_back(Op.getOperand(i)); - SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], NumOperands); + SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); DAG.ReplaceAllUsesWith(Op, New); return SDValue(New.getNode(), 1); } @@ -5740,8 +5740,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { Cond = EmitTest(Cond, X86::COND_NE, DAG); } - const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), - MVT::Flag); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); SmallVector Ops; // X86ISD::CMOV means set the result (which is operand 1) to the RHS if // condition is true. @@ -5749,7 +5748,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { Ops.push_back(Op.getOperand(1)); Ops.push_back(CC); Ops.push_back(Cond); - return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size()); + return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size()); } // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or