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Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.
llvm-svn: 16518
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@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td"
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<i64, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
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def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5,
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G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, O7,
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