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[AArch64] Remove q and non-q intrinsic definitions in the NEON scalar reduce
pairwise implementation, using an overloaded definition instead. llvm-svn: 196831
This commit is contained in:
Chad Rosier
parent
a917cd15ae
commit
850366132e
@ -107,9 +107,6 @@ def int_aarch64_neon_vuqrshrn : Neon_N2V_Narrow_Intrinsic;
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class Neon_Across_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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class Neon_2Arg_Across_Float_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_saddlv : Neon_Across_Intrinsic;
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def int_aarch64_neon_uaddlv : Neon_Across_Intrinsic;
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def int_aarch64_neon_smaxv : Neon_Across_Intrinsic;
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@ -233,29 +230,19 @@ def int_aarch64_neon_vqrshlu : Neon_2Arg_Intrinsic;
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def int_aarch64_neon_vpadd :
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Intrinsic<[llvm_v1i64_ty], [llvm_v2i64_ty],[IntrNoMem]>;
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def int_aarch64_neon_vpfadd :
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Intrinsic<[llvm_v1f32_ty], [llvm_v2f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpfaddq :
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Intrinsic<[llvm_v1f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// Scalar Reduce Pairwise Floating Point Max/Min.
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def int_aarch64_neon_vpmax :
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Intrinsic<[llvm_v1f32_ty], [llvm_v2f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpmaxq :
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Intrinsic<[llvm_v1f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpmin :
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Intrinsic<[llvm_v1f32_ty], [llvm_v2f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpminq :
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Intrinsic<[llvm_v1f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// Scalar Reduce Pairwise Floating Point Maxnm/Minnm.
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def int_aarch64_neon_vpfmaxnm :
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Intrinsic<[llvm_v1f32_ty], [llvm_v2f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpfmaxnmq :
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Intrinsic<[llvm_v1f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpfminnm :
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Intrinsic<[llvm_v1f32_ty], [llvm_v2f32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vpfminnmq :
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Intrinsic<[llvm_v1f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// Scalar Signed Integer Convert To Floating-point
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def int_aarch64_neon_vcvtf32_s32 :
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@ -5307,35 +5307,34 @@ defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
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// Scalar Reduce minNum Pairwise (Floating Point)
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defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
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multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
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SDPatternOperator opnodeD,
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multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
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def : Pat<(v1f32 (opnode (v2f32 VPR64:$Rn))),
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(INSTS VPR64:$Rn)>;
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def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
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def : Pat<(v1f64 (opnode (v2f64 VPR128:$Rn))),
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(INSTD VPR128:$Rn)>;
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}
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
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int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
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FADDPvv_S_2S, FADDPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
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int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
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FMAXPvv_S_2S, FMAXPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
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int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
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FMINPvv_S_2S, FMINPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
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int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
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FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
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int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vaddv,
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int_aarch64_neon_vaddv, FADDPvv_S_2S, FADDPvv_D_2D>;
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FADDPvv_S_2S, FADDPvv_D_2D>;
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def : Pat<(v1f32 (int_aarch64_neon_vaddv (v4f32 VPR128:$Rn))),
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(FADDPvv_S_2S (v2f32
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@ -5344,16 +5343,16 @@ def : Pat<(v1f32 (int_aarch64_neon_vaddv (v4f32 VPR128:$Rn))),
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sub_64)))>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxv,
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int_aarch64_neon_vmaxv, FMAXPvv_S_2S, FMAXPvv_D_2D>;
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FMAXPvv_S_2S, FMAXPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminv,
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int_aarch64_neon_vminv, FMINPvv_S_2S, FMINPvv_D_2D>;
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FMINPvv_S_2S, FMINPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxnmv,
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int_aarch64_neon_vmaxnmv, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
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FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminnmv,
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int_aarch64_neon_vminnmv, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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// Scalar by element Arithmetic
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@ -4,101 +4,100 @@ declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
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define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
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; CHECK: test_addp_v1i64:
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%val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
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; CHECK: addp d0, v0.2d
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ret <1 x i64> %val
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
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ret <1 x i64> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfadd(<2 x float>)
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declare <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_faddp_v1f32(<2 x float> %a) {
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; CHECK: test_faddp_v1f32:
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%val = call <1 x float> @llvm.aarch64.neon.vpfadd(<2 x float> %a)
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; CHECK: faddp s0, v0.2s
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ret <1 x float> %val
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfaddq(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_faddp_v1f64(<2 x double> %a) {
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; CHECK: test_faddp_v1f64:
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%val = call <1 x double> @llvm.aarch64.neon.vpfaddq(<2 x double> %a)
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; CHECK: faddp d0, v0.2d
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ret <1 x double> %val
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; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpmax(<2 x float>)
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declare <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fmaxp_v1f32(<2 x float> %a) {
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; CHECK: test_fmaxp_v1f32:
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%val = call <1 x float> @llvm.aarch64.neon.vpmax(<2 x float> %a)
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; CHECK: fmaxp s0, v0.2s
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ret <1 x float> %val
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; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpmaxq(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fmaxp_v1f64(<2 x double> %a) {
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; CHECK: test_fmaxp_v1f64:
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%val = call <1 x double> @llvm.aarch64.neon.vpmaxq(<2 x double> %a)
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; CHECK: fmaxp d0, v0.2d
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ret <1 x double> %val
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; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpmin(<2 x float>)
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declare <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fminp_v1f32(<2 x float> %a) {
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; CHECK: test_fminp_v1f32:
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%val = call <1 x float> @llvm.aarch64.neon.vpmin(<2 x float> %a)
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; CHECK: fminp s0, v0.2s
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ret <1 x float> %val
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; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpminq(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fminp_v1f64(<2 x double> %a) {
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; CHECK: test_fminp_v1f64:
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%val = call <1 x double> @llvm.aarch64.neon.vpminq(<2 x double> %a)
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; CHECK: fminp d0, v0.2d
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ret <1 x double> %val
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; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfmaxnm(<2 x float>)
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declare <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fmaxnmp_v1f32(<2 x float> %a) {
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; CHECK: test_fmaxnmp_v1f32:
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%val = call <1 x float> @llvm.aarch64.neon.vpfmaxnm(<2 x float> %a)
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; CHECK: fmaxnmp s0, v0.2s
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ret <1 x float> %val
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; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfmaxnmq(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fmaxnmp_v1f64(<2 x double> %a) {
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; CHECK: test_fmaxnmp_v1f64:
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%val = call <1 x double> @llvm.aarch64.neon.vpfmaxnmq(<2 x double> %a)
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; CHECK: fmaxnmp d0, v0.2d
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ret <1 x double> %val
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; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfminnm(<2 x float>)
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declare <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fminnmp_v1f32(<2 x float> %a) {
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; CHECK: test_fminnmp_v1f32:
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%val = call <1 x float> @llvm.aarch64.neon.vpfminnm(<2 x float> %a)
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; CHECK: fminnmp s0, v0.2s
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ret <1 x float> %val
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; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfminnmq(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fminnmp_v1f64(<2 x double> %a) {
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; CHECK: test_fminnmp_v1f64:
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%val = call <1 x double> @llvm.aarch64.neon.vpfminnmq(<2 x double> %a)
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; CHECK: fminnmp d0, v0.2d
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ret <1 x double> %val
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; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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define float @test_vaddv_f32(<2 x float> %a) {
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