From 8b4a359a597ac3dfbfff517a2c640bc995306e98 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Mon, 18 Feb 2013 04:55:38 +0000 Subject: [PATCH] Expand pseudo/macro BteqzT8SltuX16 . There is no test case because at this time, llvm is generating a different but equivalent pattern that would lead to this instruction. I am trying to think of a way to get it to generate this. If I can't, I may just remove the pseudo. llvm-svn: 175419 --- lib/Target/Mips/Mips16InstrInfo.cpp | 5 +++++ lib/Target/Mips/Mips16InstrInfo.td | 2 ++ 2 files changed, 7 insertions(+) diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index ba1002ed4ca..e0277ff5a00 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -142,6 +142,11 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BteqzT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16); break; + case Mips::BteqzT8SltuX16: + // TBD: figure out a way to get this or remove the instruction + // altogether. + ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16); + break; case Mips::BtnezT8CmpX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16); break; diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 2ab7b477245..c7adce3a5ba 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -1012,6 +1012,8 @@ def SltCCRxRy16: FCCRR16_ins<"slt">; // Purpose: Set on Less Than Unsigned // To record the result of an unsigned less-than comparison. // +def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>; + def SltuRxRyRz16: FRRTR16_ins<"sltu"> { let isCodeGenOnly=1; }