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[RISCV] Add machine function pass to merge base + offset
Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 llvm-svn: 335786
This commit is contained in:
Sameer AbuAsal
parent
ca4ba5cdc7
commit
92233f14e9
@ -20,6 +20,7 @@ add_llvm_target(RISCVCodeGen
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterInfo.cpp
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RISCVSubtarget.cpp
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RISCVTargetMachine.cpp
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@ -25,6 +25,7 @@ class MCInst;
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class MCOperand;
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class MachineInstr;
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class MachineOperand;
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class PassRegistry;
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void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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const AsmPrinter &AP);
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@ -32,6 +33,9 @@ bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp, const AsmPrinter &AP);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
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FunctionPass *createRISCVMergeBaseOffsetOptPass();
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void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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}
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#endif
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@ -56,14 +56,12 @@ public:
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private:
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void doPeepholeLoadStoreADDI();
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void doPeepholeGlobalAddiLuiOffset();
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void doPeepholeBuildPairF64SplitF64();
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};
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}
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void RISCVDAGToDAGISel::PostprocessISelDAG() {
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doPeepholeLoadStoreADDI();
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doPeepholeGlobalAddiLuiOffset();
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doPeepholeBuildPairF64SplitF64();
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}
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@ -130,212 +128,6 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
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return false;
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}
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// Detect the pattern lui %hi(global) --> ADDI %lo(global)
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// HiLUI LoADDI
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static bool detectLuiAddiGlobal(SDNode *Tail, unsigned &Idx, SDValue &LoADDI,
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SDValue &HiLUI, GlobalAddressSDNode *&GAlo,
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GlobalAddressSDNode *&GAhi) {
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// Try to detect the pattern on every operand of the tail instruction.
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for (Idx = 0; Idx < Tail->getNumOperands(); Idx++) {
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LoADDI = Tail->getOperand(Idx);
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// LoADDI should only be used by one instruction (Tail).
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if (!LoADDI->isMachineOpcode() ||
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!(LoADDI->getMachineOpcode() == RISCV::ADDI) ||
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!isa<GlobalAddressSDNode>(LoADDI->getOperand(1)) ||
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!LoADDI->hasOneUse())
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continue;
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// Check for existence of %lo target flag.
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GAlo = cast<GlobalAddressSDNode>(LoADDI->getOperand(1));
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if (!(GAlo->getTargetFlags() == RISCVII::MO_LO) ||
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!(GAlo->getOffset() == 0))
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return false;
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// Check for existence of %hi target flag.
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HiLUI = LoADDI->getOperand(0);
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if (!HiLUI->isMachineOpcode() ||
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!(HiLUI->getMachineOpcode() == RISCV::LUI) ||
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!isa<GlobalAddressSDNode>(HiLUI->getOperand(0)) || !HiLUI->hasOneUse())
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return false;
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GAhi = cast<GlobalAddressSDNode>(HiLUI->getOperand(0));
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if (!(GAhi->getTargetFlags() == RISCVII::MO_HI) ||
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!(GAhi->getOffset() == 0))
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return false;
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return true;
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}
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return false;
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}
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static bool matchLuiOffset(SDValue &OffsetLUI, int64_t &Offset) {
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if (!OffsetLUI->isMachineOpcode() ||
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!(OffsetLUI->getMachineOpcode() == RISCV::LUI) ||
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!isa<ConstantSDNode>(OffsetLUI->getOperand(0)))
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return false;
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Offset = cast<ConstantSDNode>(OffsetLUI->getOperand(0))->getSExtValue();
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Offset = Offset << 12;
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LLVM_DEBUG(dbgs() << " Detected \" LUI Offset_hi\"\n");
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return true;
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}
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static bool matchAddiLuiOffset(SDValue &OffsetLoADDI, int64_t &Offset) {
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// LoADDI should only be used by the tail instruction only.
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if (!OffsetLoADDI->isMachineOpcode() ||
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!(OffsetLoADDI->getMachineOpcode() == RISCV::ADDI) ||
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!isa<ConstantSDNode>(OffsetLoADDI->getOperand(1)) ||
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!OffsetLoADDI->hasOneUse())
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return false;
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int64_t OffLo =
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cast<ConstantSDNode>(OffsetLoADDI->getOperand(1))->getZExtValue();
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// HiLUI should only be used by the loADDI.
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SDValue OffsetHiLUI = (OffsetLoADDI->getOperand(0));
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if (!OffsetHiLUI->isMachineOpcode() ||
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!(OffsetHiLUI->getMachineOpcode() == RISCV::LUI) ||
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!isa<ConstantSDNode>(OffsetHiLUI->getOperand(0)) ||
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!OffsetHiLUI->hasOneUse())
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return false;
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int64_t OffHi =
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cast<ConstantSDNode>(OffsetHiLUI->getOperand(0))->getSExtValue();
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Offset = (OffHi << 12) + OffLo;
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LLVM_DEBUG(dbgs() << " Detected \" ADDI (LUI Offset_hi), Offset_lo\"\n");
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return true;
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}
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static void updateTailInstrUsers(SDNode *Tail, SelectionDAG *CurDAG,
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GlobalAddressSDNode *GAhi,
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GlobalAddressSDNode *GAlo,
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SDValue &GlobalHiLUI, SDValue &GlobalLoADDI,
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int64_t Offset) {
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// Update the offset in GAhi and GAlo.
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SDLoc DL(Tail->getOperand(1));
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SDValue GAHiNew = CurDAG->getTargetGlobalAddress(GAhi->getGlobal(), DL,
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GlobalHiLUI.getValueType(),
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Offset, RISCVII::MO_HI);
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SDValue GALoNew = CurDAG->getTargetGlobalAddress(GAlo->getGlobal(), DL,
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GlobalLoADDI.getValueType(),
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Offset, RISCVII::MO_LO);
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CurDAG->UpdateNodeOperands(GlobalHiLUI.getNode(), GAHiNew);
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CurDAG->UpdateNodeOperands(GlobalLoADDI.getNode(), GlobalHiLUI, GALoNew);
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// Update all uses of the Tail with the GlobalLoADDI. After
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// this Tail will be a dead node.
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SDValue From = SDValue(Tail, 0);
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CurDAG->ReplaceAllUsesOfValuesWith(&From, &GlobalLoADDI, 1);
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}
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// TODO: This transformation might be better implemeted in a Machine Funtion
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// Pass as discussed here: https://reviews.llvm.org/D45748.
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//
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// Merge the offset of address calculation into the offset field
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// of a global address node in a global address lowering sequence ("LUI
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// %hi(global) --> add %lo(global)") under the following conditions: 1) The
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// offset field in the global address lowering sequence is zero. 2) The lowered
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// global address is only used in one node, referred to as "Tail".
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// This peephole does the following transformations to merge the offset:
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// 1) ADDI (ADDI (LUI %hi(global)) %lo(global)), offset
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// --->
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// ADDI (LUI %hi(global + offset)) %lo(global + offset).
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//
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// This generates:
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// lui a0, hi (global + offset)
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// add a0, a0, lo (global + offset)
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// Instead of
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// lui a0, hi (global)
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// addi a0, hi (global)
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// addi a0, offset
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// This pattern is for cases when the offset is small enough to fit in the
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// immediate filed of ADDI (less than 12 bits).
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// 2) ADD ((ADDI (LUI %hi(global)) %lo(global)), (LUI hi_offset))
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// --->
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// offset = hi_offset << 12
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// ADDI (LUI %hi(global + offset)) %lo(global + offset)
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// Which generates the ASM:
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// lui a0, hi(global + offset)
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// addi a0, lo(global + offset)
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// Instead of:
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// lui a0, hi(global)
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// addi a0, lo(global)
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// lui a1, (offset)
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// add a0, a0, a1
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// This pattern is for cases when the offset doesn't fit in an immediate field
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// of ADDI but the lower 12 bits are all zeros.
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// 3) ADD ((ADDI (LUI %hi(global)) %lo(global)), (ADDI lo_offset, (LUI
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// hi_offset)))
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// --->
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// ADDI (LUI %hi(global + offset)) %lo(global + offset)
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// Which generates the ASM:
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// lui a1, %hi(global + offhi20<<12 + offlo12)
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// addi a1, %lo(global + offhi20<<12 + offlo12)
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// Instead of:
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// lui a0, hi(global)
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// addi a0, lo(global)
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// lui a1, (offhi20)
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// addi a1, (offlo12)
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// add a0, a0, a1
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// This pattern is for cases when the offset doesn't fit in an immediate field
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// of ADDI and both the lower 1 bits and high 20 bits are non zero.
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void RISCVDAGToDAGISel::doPeepholeGlobalAddiLuiOffset() {
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SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
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++Position;
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SelectionDAG::allnodes_iterator Begin(CurDAG->allnodes_begin());
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while (Position != Begin) {
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SDNode *Tail = &*--Position;
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// Skip dead nodes and any non-machine opcodes.
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if (Tail->use_empty() || !Tail->isMachineOpcode())
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continue;
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// The tail instruction can be an ADD or an ADDI.
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if (!Tail->isMachineOpcode() || !(Tail->getMachineOpcode() == RISCV::ADD ||
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Tail->getMachineOpcode() == RISCV::ADDI))
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continue;
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// First detect the global address part of pattern:
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// (lui %hi(global) --> Addi %lo(global))
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unsigned GlobalLoADDiIdx;
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SDValue GlobalLoADDI;
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SDValue GlobalHiLUI;
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GlobalAddressSDNode *GAhi;
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GlobalAddressSDNode *GAlo;
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if (!detectLuiAddiGlobal(Tail, GlobalLoADDiIdx, GlobalLoADDI, GlobalHiLUI,
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GAlo, GAhi))
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continue;
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LLVM_DEBUG(dbgs() << " Detected \"ADDI LUI %hi(global), %lo(global)\n");
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// Detect the offset part for the address calculation by looking at the
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// other operand of the tail instruction:
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int64_t Offset;
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if (Tail->getMachineOpcode() == RISCV::ADD) {
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// If the Tail is an ADD instruction, the offset can be in two forms:
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// 1) LUI hi_Offset followed by:
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// ADDI lo_offset
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// This happens in case the offset has non zero bits in
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// both hi 20 and lo 12 bits.
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// 2) LUI (offset20)
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// This happens in case the lower 12 bits of the offset are zeros.
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SDValue OffsetVal = Tail->getOperand(1 - GlobalLoADDiIdx);
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if (!matchAddiLuiOffset(OffsetVal, Offset) &&
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!matchLuiOffset(OffsetVal, Offset))
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continue;
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} else
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// The Tail is an ADDI instruction:
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Offset = cast<ConstantSDNode>(Tail->getOperand(1 - GlobalLoADDiIdx))
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->getSExtValue();
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LLVM_DEBUG(
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dbgs()
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<< " Fold offset value into global offset of LUI %hi and ADDI %lo\n");
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LLVM_DEBUG(dbgs() << "\tTail:");
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LLVM_DEBUG(Tail->dump(CurDAG));
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LLVM_DEBUG(dbgs() << "\tGlobalHiLUI:");
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LLVM_DEBUG(GlobalHiLUI->dump(CurDAG));
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LLVM_DEBUG(dbgs() << "\tGlobalLoADDI:");
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LLVM_DEBUG(GlobalLoADDI->dump(CurDAG));
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LLVM_DEBUG(dbgs() << "\n");
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updateTailInstrUsers(Tail, CurDAG, GAhi, GAlo, GlobalHiLUI, GlobalLoADDI,
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Offset);
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}
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CurDAG->RemoveDeadNodes();
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}
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// Merge an ADDI into the offset of a load/store instruction where possible.
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// (load (add base, off), 0) -> (load base, off)
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// (store val, (add base, off)) -> (store val, base, off)
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286
lib/Target/RISCV/RISCVMergeBaseOffset.cpp
Normal file
286
lib/Target/RISCV/RISCVMergeBaseOffset.cpp
Normal file
@ -0,0 +1,286 @@
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//===----- RISCVMergeBaseOffset.cpp - Optimise address calculations ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Merge the offset of address calculation into the offset field
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// of instructions in a global address lowering sequence. This pass transforms:
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// lui vreg1, %hi(s)
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// addi vreg2, vreg1, %lo(s)
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// addi vreg3, verg2, Offset
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//
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// Into:
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// lui vreg1, %hi(s+Offset)
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// addi vreg2, vreg1, %lo(s+Offset)
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//
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// The transformation is carried out under certain conditions:
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// 1) The offset field in the base of global address lowering sequence is zero.
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// 2) The lowered global address has only one use.
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//
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// The offset field can be in a different form. This pass handles all of them.
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include <set>
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using namespace llvm;
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#define DEBUG_TYPE "riscv-merge-base-offset"
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#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
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namespace {
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struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
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static char ID;
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const MachineFunction *MF;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
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bool detectAndFoldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI);
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void foldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI, MachineInstr &Tail,
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int64_t Offset);
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bool matchLargeOffset(MachineInstr &TailAdd, unsigned GSReg, int64_t &Offset);
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RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::IsSSA);
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}
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StringRef getPassName() const override {
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return RISCV_MERGE_BASE_OFFSET_NAME;
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}
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private:
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MachineRegisterInfo *MRI;
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std::set<MachineInstr *> DeadInstrs;
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};
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}; // end anonymous namespace
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char RISCVMergeBaseOffsetOpt::ID = 0;
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INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, "riscv-merge-base-offset",
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RISCV_MERGE_BASE_OFFSET_NAME, false, false)
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// Detect the pattern:
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// lui vreg1, %hi(s)
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// addi vreg2, vreg1, %lo(s)
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//
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// Pattern only accepted if:
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// 1) ADDI has only one use.
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// 2) LUI has only one use; which is the ADDI.
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// 3) Both ADDI and LUI have GlobalAddress type which indicates that these
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// are generated from global address lowering.
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// 4) Offset value in the Global Address is 0.
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bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
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MachineInstr *&LoADDI) {
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if (HiLUI.getOpcode() != RISCV::LUI ||
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HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
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HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
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HiLUI.getOperand(1).getOffset() != 0 ||
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!MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
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return false;
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unsigned HiLuiDestReg = HiLUI.getOperand(0).getReg();
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LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
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if (LoADDI->getOpcode() != RISCV::ADDI ||
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LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
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LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
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LoADDI->getOperand(2).getOffset() != 0 ||
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!MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
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return false;
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return true;
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}
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// Update the offset in HiLUI and LoADDI instructions.
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// Delete the tail instruction and update all the uses to use the
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// output from LoADDI.
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void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &HiLUI,
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MachineInstr &LoADDI,
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MachineInstr &Tail, int64_t Offset) {
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// Put the offset back in HiLUI and the LoADDI
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HiLUI.getOperand(1).setOffset(Offset);
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LoADDI.getOperand(2).setOffset(Offset);
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// Delete the tail instruction.
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DeadInstrs.insert(&Tail);
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MRI->replaceRegWith(Tail.getOperand(0).getReg(),
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LoADDI.getOperand(0).getReg());
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LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n"
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<< " " << HiLUI << " " << LoADDI;);
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}
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// Detect patterns for large offsets that are passed into an ADD instruction.
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//
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// Base address lowering is of the form:
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// HiLUI: lui vreg1, %hi(s)
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// LoADDI: addi vreg2, vreg1, %lo(s)
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// / \
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// / \
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// / \
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// / The large offset can be of two forms: \
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// 1) Offset that has non zero bits in lower 2) Offset that has non zero
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// 12 bits and upper 20 bits bits in upper 20 bits only
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// OffseLUI: lui vreg3, 4
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// OffsetTail: addi voff, vreg3, 188 OffsetTail: lui voff, 128
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// \ /
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// \ /
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// \ /
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// \ /
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// TailAdd: add vreg4, vreg2, voff
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bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
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unsigned GAReg,
|
||||
int64_t &Offset) {
|
||||
assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
|
||||
unsigned Rs = TailAdd.getOperand(1).getReg();
|
||||
unsigned Rt = TailAdd.getOperand(2).getReg();
|
||||
unsigned Reg = Rs == GAReg ? Rt : Rs;
|
||||
|
||||
// Can't fold if the register has more than one use.
|
||||
if (!MRI->hasOneUse(Reg))
|
||||
return false;
|
||||
// This can point to an ADDI or a LUI:
|
||||
MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
|
||||
if (OffsetTail.getOpcode() == RISCV::ADDI) {
|
||||
// The offset value has non zero bits in both %hi and %lo parts.
|
||||
// Detect an ADDI that feeds from a LUI instruction.
|
||||
MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
|
||||
if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
|
||||
return false;
|
||||
int64_t OffLo = AddiImmOp.getImm();
|
||||
MachineInstr &OffsetLui =
|
||||
*MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
|
||||
MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
|
||||
if (OffsetLui.getOpcode() != RISCV::LUI ||
|
||||
LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
|
||||
!MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
|
||||
return false;
|
||||
int64_t OffHi = OffsetLui.getOperand(1).getImm();
|
||||
Offset = (OffHi << 12) + OffLo;
|
||||
LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail
|
||||
<< " " << OffsetLui);
|
||||
DeadInstrs.insert(&OffsetTail);
|
||||
DeadInstrs.insert(&OffsetLui);
|
||||
return true;
|
||||
} else if (OffsetTail.getOpcode() == RISCV::LUI) {
|
||||
// The offset value has all zero bits in the lower 12 bits. Only LUI
|
||||
// exists.
|
||||
LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail);
|
||||
Offset = OffsetTail.getOperand(1).getImm() << 12;
|
||||
DeadInstrs.insert(&OffsetTail);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
|
||||
MachineInstr &LoADDI) {
|
||||
unsigned DestReg = LoADDI.getOperand(0).getReg();
|
||||
assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI");
|
||||
// LoADDI has only one use.
|
||||
MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent();
|
||||
switch (Tail.getOpcode()) {
|
||||
default:
|
||||
LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
|
||||
<< Tail);
|
||||
return false;
|
||||
case RISCV::ADDI: {
|
||||
// Offset is simply an immediate operand.
|
||||
int64_t Offset = Tail.getOperand(2).getImm();
|
||||
LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail);
|
||||
foldOffset(HiLUI, LoADDI, Tail, Offset);
|
||||
return true;
|
||||
} break;
|
||||
case RISCV::ADD: {
|
||||
// The offset is too large to fit in the immediate field of ADDI.
|
||||
// This can be in two forms:
|
||||
// 1) LUI hi_Offset followed by:
|
||||
// ADDI lo_offset
|
||||
// This happens in case the offset has non zero bits in
|
||||
// both hi 20 and lo 12 bits.
|
||||
// 2) LUI (offset20)
|
||||
// This happens in case the lower 12 bits of the offset are zeros.
|
||||
int64_t Offset;
|
||||
if (!matchLargeOffset(Tail, DestReg, Offset))
|
||||
return false;
|
||||
foldOffset(HiLUI, LoADDI, Tail, Offset);
|
||||
return true;
|
||||
} break;
|
||||
case RISCV::LB:
|
||||
case RISCV::LH:
|
||||
case RISCV::LW:
|
||||
case RISCV::LBU:
|
||||
case RISCV::LHU:
|
||||
case RISCV::LWU:
|
||||
case RISCV::LD:
|
||||
case RISCV::FLW:
|
||||
case RISCV::FLD:
|
||||
case RISCV::SB:
|
||||
case RISCV::SH:
|
||||
case RISCV::SW:
|
||||
case RISCV::SD:
|
||||
case RISCV::FSW:
|
||||
case RISCV::FSD: {
|
||||
// Transforms the sequence: Into:
|
||||
// HiLUI: lui vreg1, %hi(foo) ---> lui vreg1, %hi(foo+8)
|
||||
// LoADDI: addi vreg2, vreg1, %lo(foo) ---> lw vreg3, lo(foo+8)(vreg1)
|
||||
// Tail: lw vreg3, 8(vreg2)
|
||||
if (Tail.getOperand(1).isFI())
|
||||
return false;
|
||||
// Register defined by LoADDI should be used in the base part of the
|
||||
// load\store instruction. Otherwise, no folding possible.
|
||||
unsigned BaseAddrReg = Tail.getOperand(1).getReg();
|
||||
if (DestReg != BaseAddrReg)
|
||||
return false;
|
||||
MachineOperand &TailImmOp = Tail.getOperand(2);
|
||||
int64_t Offset = TailImmOp.getImm();
|
||||
// Update the offsets in global address lowering.
|
||||
HiLUI.getOperand(1).setOffset(Offset);
|
||||
// Update the immediate in the Tail instruction to add the offset.
|
||||
Tail.RemoveOperand(2);
|
||||
MachineOperand &ImmOp = LoADDI.getOperand(2);
|
||||
ImmOp.setOffset(Offset);
|
||||
Tail.addOperand(ImmOp);
|
||||
// Update the base reg in the Tail instruction to feed from LUI.
|
||||
// Output of HiLUI is only used in LoADDI, no need to use
|
||||
// MRI->replaceRegWith().
|
||||
Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
|
||||
DeadInstrs.insert(&LoADDI);
|
||||
return true;
|
||||
} break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
|
||||
if (skipFunction(Fn.getFunction()))
|
||||
return false;
|
||||
|
||||
DeadInstrs.clear();
|
||||
MRI = &Fn.getRegInfo();
|
||||
for (MachineBasicBlock &MBB : Fn) {
|
||||
LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
|
||||
for (MachineInstr &HiLUI : MBB) {
|
||||
MachineInstr *LoADDI = nullptr;
|
||||
if (!detectLuiAddiGlobal(HiLUI, LoADDI))
|
||||
continue;
|
||||
LLVM_DEBUG(dbgs() << " Found lowered global address with one use: "
|
||||
<< *LoADDI->getOperand(2).getGlobal() << "\n");
|
||||
// If the use count is only one, merge the offset
|
||||
detectAndFoldOffset(HiLUI, *LoADDI);
|
||||
}
|
||||
}
|
||||
// Delete dead instructions.
|
||||
for (auto *MI : DeadInstrs)
|
||||
MI->eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Returns an instance of the Merge Base Offset Optimization pass.
|
||||
FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() {
|
||||
return new RISCVMergeBaseOffsetOpt();
|
||||
}
|
||||
@ -78,6 +78,7 @@ public:
|
||||
void addIRPasses() override;
|
||||
bool addInstSelector() override;
|
||||
void addPreEmitPass() override;
|
||||
void addPreRegAlloc() override;
|
||||
};
|
||||
}
|
||||
|
||||
@ -97,3 +98,7 @@ bool RISCVPassConfig::addInstSelector() {
|
||||
}
|
||||
|
||||
void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
|
||||
|
||||
void RISCVPassConfig::addPreRegAlloc() {
|
||||
addPass(createRISCVMergeBaseOffsetOptPass());
|
||||
}
|
||||
|
||||
@ -49,6 +49,23 @@ if.end: ; preds = %if.then, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
; This test checks that the offset is reconstructed correctly when
|
||||
; "addi" of the big offset has a negative immediate.
|
||||
; without peephole this generates:
|
||||
; lui a1, %hi(g)
|
||||
; addi a1, a0, %lo(g)
|
||||
; lui a0, 18 ---> offset
|
||||
; addi a0, a0, -160
|
||||
; add a0, a0, a1 ---> base + offset.
|
||||
define i8* @big_offset_neg_addi() {
|
||||
; CHECK-LABEL: big_offset_neg_addi:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lui a0, %hi(g+73568)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(g+73568)
|
||||
; CHECK-NEXT: ret
|
||||
ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 73568)
|
||||
}
|
||||
|
||||
; This test checks for the case where the offset is only an LUI.
|
||||
; without peephole this generates:
|
||||
; lui a0, %hi(g)
|
||||
@ -84,36 +101,19 @@ entry:
|
||||
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1)
|
||||
}
|
||||
|
||||
; TODO: In this case we get a better sequence if the offset didn't get didn't
|
||||
; get merged back in %if.end and %if.then. The current peephole is not able to
|
||||
; detect the shared global address node across blocks.
|
||||
; Without the peephole we can generate:
|
||||
;# %bb.0: # %entry
|
||||
; lui a0, %hi(s)
|
||||
; addi a0, a0, %lo(s)
|
||||
; lw a1, 164(a0)
|
||||
; beqz a1, .LBB0_2
|
||||
;# %bb.1: # %if.end
|
||||
; addi a0, a0, 168
|
||||
; ret
|
||||
;.LBB0_2: # %if.then
|
||||
; addi a0, a0, 160
|
||||
; ret
|
||||
; Function Attrs: norecurse nounwind optsize readonly
|
||||
define dso_local i32* @control_flow_no_mem(i32 %n) local_unnamed_addr #1 {
|
||||
; CHECK-LABEL: control_flow_no_mem:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lui a0, %hi(s)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(s)
|
||||
; CHECK-NEXT: lw a0, 164(a0)
|
||||
; CHECK-NEXT: beqz a0, .LBB5_2
|
||||
; CHECK-NEXT: lw a1, 164(a0)
|
||||
; CHECK-NEXT: beqz a1, .LBB6_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: lui a0, %hi(s+168)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(s+168)
|
||||
; CHECK-NEXT: addi a0, a0, 168
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .LBB5_2: # %if.then
|
||||
; CHECK-NEXT: lui a0, %hi(s+160)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(s+160)
|
||||
; CHECK-NEXT: .LBB6_2: # %if.then
|
||||
; CHECK-NEXT: addi a0, a0, 160
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 2), align 4
|
||||
@ -125,32 +125,21 @@ if.end: ; preds = %if.then, %entry
|
||||
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 3)
|
||||
}
|
||||
|
||||
;TODO: Offset shouln't be separated in this case. We get shorter sequence if it
|
||||
; is merged in the LUI %hi and the ADDI %lo, the "ADDI" could be folded in the
|
||||
; immediate part of "lhu" genertating the sequence:
|
||||
; lui a0, %hi(foo +8)
|
||||
; lhu a0, %lo(foo+8)(a0)
|
||||
; instead of:
|
||||
; lui a0, %hi(foo)
|
||||
; addi a0, a0, %lo(foo)
|
||||
; lhu a0, 8(a0)
|
||||
|
||||
define dso_local i32 @load_half() nounwind {
|
||||
; CHECK-LABEL: load_half:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addi sp, sp, -16
|
||||
; CHECK-NEXT: sw ra, 12(sp)
|
||||
; CHECK-NEXT: lui a0, %hi(foo)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(foo)
|
||||
; CHECK-NEXT: lhu a0, 8(a0)
|
||||
; CHECK-NEXT: lui a0, %hi(foo+8)
|
||||
; CHECK-NEXT: lhu a0, %lo(foo+8)(a0)
|
||||
; CHECK-NEXT: addi a1, zero, 140
|
||||
; CHECK-NEXT: bne a0, a1, .LBB6_2
|
||||
; CHECK-NEXT: bne a0, a1, .LBB7_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.end
|
||||
; CHECK-NEXT: mv a0, zero
|
||||
; CHECK-NEXT: lw ra, 12(sp)
|
||||
; CHECK-NEXT: addi sp, sp, 16
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .LBB6_2: # %if.then
|
||||
; CHECK-NEXT: .LBB7_2: # %if.then
|
||||
; CHECK-NEXT: call abort
|
||||
entry:
|
||||
%0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2
|
||||
@ -166,3 +155,15 @@ if.end:
|
||||
}
|
||||
|
||||
declare void @abort()
|
||||
|
||||
define dso_local void @one_store() local_unnamed_addr {
|
||||
; CHECK-LABEL: one_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lui a0, %hi(s+160)
|
||||
; CHECK-NEXT: addi a1, zero, 10
|
||||
; CHECK-NEXT: sw a1, %lo(s+160)(a0)
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user