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[X86] Fix missing/wrong scheduling model found by code inspection.

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llvm-svn: 207014
This commit is contained in:
Quentin Colombet 2014-04-23 19:30:26 +00:00
parent 06fc6f472d
commit 92e7065bf4
2 changed files with 4 additions and 1 deletions
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3
lib/Target/X86/X86InstrMMX.td
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@ -267,11 +267,12 @@ def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}", "movq\t{$src, $dst|$dst, $src}",
[(set VR64:$dst, (load_mmx addr:$src))], [(set VR64:$dst, (load_mmx addr:$src))],
IIC_MMX_MOVQ_RM>; IIC_MMX_MOVQ_RM>;
} // SchedRW
let SchedRW = [WriteStore] in
def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movq\t{$src, $dst|$dst, $src}", "movq\t{$src, $dst|$dst, $src}",
[(store (x86mmx VR64:$src), addr:$dst)], [(store (x86mmx VR64:$src), addr:$dst)],
IIC_MMX_MOVQ_RM>; IIC_MMX_MOVQ_RM>;
} // SchedRW
let SchedRW = [WriteMove] in { let SchedRW = [WriteMove] in {
def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),

2
lib/Target/X86/X86InstrSSE.td
View File

@ -7407,6 +7407,7 @@ let Predicates = [UseSSE41] in {
} }
let SchedRW = [WriteLoad] in {
let Predicates = [HasAVX] in let Predicates = [HasAVX] in
def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}", "vmovntdqa\t{$src, $dst|$dst, $src}",
@ -7420,6 +7421,7 @@ def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"movntdqa\t{$src, $dst|$dst, $src}", "movntdqa\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>; [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
} // SchedRW
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SSE4.2 - Compare Instructions // SSE4.2 - Compare Instructions