RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-13 14:35:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Move the DataLayout to the generic TargetMachine, making it mandatory.

Browse Source 
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
This commit is contained in:
Mehdi Amini 2015-03-12 00:07:24 +00:00
parent 49cd81f1f5
commit 94c8770ed5
30 changed files with 93 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
include/llvm/Target/TargetMachine.h
View File

@ -15,6 +15,7 @@
#define LLVM_TARGET_TARGETMACHINE_H
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetOptions.h"
@ -62,12 +63,16 @@ class TargetMachine {
TargetMachine(const TargetMachine &) = delete;
void operator=(const TargetMachine &) = delete;
protected: // Can only create subclasses.
TargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS, const TargetOptions &Options);
TargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TargetTriple, StringRef CPU, StringRef FS,
const TargetOptions &Options);
/// TheTarget - The Target that this machine was created for.
const Target &TheTarget;
/// DataLayout - For ABI type size and alignment.
const DataLayout DL;
/// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
/// feature strings the TargetMachine instance is created with.
std::string TargetTriple;
@ -119,9 +124,7 @@ public:
/// getDataLayout - This method returns a pointer to the DataLayout for
/// the target. It should be unchanging for every subtarget.
virtual const DataLayout *getDataLayout() const {
return nullptr;
}
const DataLayout *getDataLayout() const { return &DL; }
/// \brief Reset the target options based on the function's attributes.
// FIXME: Remove TargetOptions that affect per-function code generation
@ -236,9 +239,9 @@ public:
///
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS, TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TargetTriple, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
void initAsmInfo();

9
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -66,12 +66,13 @@ void LLVMTargetMachine::initAsmInfo() {
AsmInfo = TmpAsmInfo;
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
TargetOptions Options,
LLVMTargetMachine::LLVMTargetMachine(const Target &T,
StringRef DataLayoutString,
StringRef Triple, StringRef CPU,
StringRef FS, TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS, Options) {
: TargetMachine(T, DataLayoutString, Triple, CPU, FS, Options) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
}

26
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -104,6 +104,16 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
return make_unique<AArch64_ELFTargetObjectFile>();
}
// Helper function to build a DataLayout string
static std::string computeDataLayout(StringRef TT, bool LittleEndian) {
Triple Triple(TT);
if (Triple.isOSBinFormatMachO())
return "e-m:o-i64:64-i128:128-n32:64-S128";
if (LittleEndian)
return "e-m:e-i64:64-i128:128-n32:64-S128";
return "E-m:e-i64:64-i128:128-n32:64-S128";
}
/// TargetMachine ctor - Create an AArch64 architecture model.
///
AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
@ -112,16 +122,14 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool LittleEndian)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
// This nested ternary is horrible, but DL needs to be properly
// initialized
// before TLInfo is constructed.
DL(Triple(TT).isOSBinFormatMachO()
? "e-m:o-i64:64-i128:128-n32:64-S128"
: (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
: "E-m:e-i64:64-i128:128-n32:64-S128")),
// This nested ternary is horrible, but DL needs to be properly
// initialized
// before TLInfo is constructed.
: LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
Subtarget(TT, CPU, FS, *this, LittleEndian),
isLittle(LittleEndian) {
initAsmInfo();
}

2
lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -23,7 +23,6 @@ namespace llvm {
class AArch64TargetMachine : public LLVMTargetMachine {
protected:
const DataLayout DL;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
AArch64Subtarget Subtarget;
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
@ -36,7 +35,6 @@ public:
~AArch64TargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const AArch64Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}

14
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -105,9 +105,11 @@ computeTargetABI(const Triple &TT, StringRef CPU,
return TargetABI;
}
static std::string computeDataLayout(const Triple &TT,
ARMBaseTargetMachine::ARMABI ABI,
static std::string computeDataLayout(StringRef TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
const Triple Triple(TT);
auto ABI = computeTargetABI(Triple, CPU, Options);
std::string Ret = "";
if (isLittle)
@ -117,7 +119,7 @@ static std::string computeDataLayout(const Triple &TT,
// Big endian.
Ret += "E";
Ret += DataLayout::getManglingComponent(TT);
Ret += DataLayout::getManglingComponent(Triple);
// Pointers are 32 bits and aligned to 32 bits.
Ret += "-p:32:32";
@ -147,7 +149,7 @@ static std::string computeDataLayout(const Triple &TT,
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else.
if (TT.isOSNaCl())
if (Triple.isOSNaCl())
Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
Ret += "-S64";
@ -164,9 +166,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
DL(computeDataLayout(Triple(TT), TargetABI, isLittle)),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {

2
lib/Target/ARM/ARMTargetMachine.h
View File

@ -30,7 +30,6 @@ public:
} TargetABI;
protected:
const DataLayout DL;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
ARMSubtarget Subtarget;
bool isLittle;
@ -47,7 +46,6 @@ public:
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
const DataLayout *getDataLayout() const override { return &DL; }
bool isLittleEndian() const { return isLittle; }
/// \brief Get the TargetIRAnalysis for this target.

4
lib/Target/BPF/BPFTargetMachine.cpp
View File

@ -35,9 +35,9 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, "e-m:e-p:64:64-i64:64-n32:64-S128", TT, CPU, FS,
Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
DL("e-m:e-p:64:64-i64:64-n32:64-S128"),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

1
lib/Target/BPF/BPFTargetMachine.h
View File

@ -20,7 +20,6 @@
namespace llvm {
class BPFTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL;
BPFSubtarget Subtarget;
public:

10
lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -26,11 +26,11 @@ class CPPSubtarget : public TargetSubtargetInfo {
};
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS, Options), Subtarget() {}
CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: TargetMachine(T, "", TT, CPU, FS, Options), Subtarget() {}
private:
CPPSubtarget Subtarget;

5
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -65,9 +65,10 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()),
DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS, *this) {
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

2
lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -24,7 +24,6 @@ class Module;
class HexagonTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL; // Calculates type size & alignment.
HexagonSubtarget Subtarget;
public:
@ -33,7 +32,6 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
~HexagonTargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const HexagonSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

5
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -30,10 +30,11 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS,
Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
// FIXME: Check DataLayout string.
DL("e-m:e-p:16:16-i32:16:32-a:16-n8:16"), Subtarget(TT, CPU, FS, *this) {
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

2
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -25,7 +25,6 @@ namespace llvm {
///
class MSP430TargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL; // Calculates type size & alignment
MSP430Subtarget Subtarget;
public:
@ -35,7 +34,6 @@ public:
CodeGenOpt::Level OL);
~MSP430TargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const MSP430Subtarget *getSubtargetImpl() const override {
return &Subtarget;
}

12
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -46,8 +46,12 @@ extern "C" void LLVMInitializeMipsTarget() {
RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
}
static std::string computeDataLayout(bool isLittle, MipsABIInfo &ABI) {
static std::string computeDataLayout(StringRef TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
std::string Ret = "";
MipsABIInfo ABI =
MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions);
// There are both little and big endian mips.
if (isLittle)
@ -86,11 +90,11 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
DL(computeDataLayout(isLittle, ABI)), Subtarget(nullptr),
DefaultSubtarget(TT, CPU, FS, isLittle, *this),
Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, *this),
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",

2
lib/Target/Mips/MipsTargetMachine.h
View File

@ -31,7 +31,6 @@ class MipsTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
// Selected ABI
MipsABIInfo ABI;
const DataLayout DL; // Calculates type size & alignment
MipsSubtarget *Subtarget;
MipsSubtarget DefaultSubtarget;
MipsSubtarget NoMips16Subtarget;
@ -47,7 +46,6 @@ public:
TargetIRAnalysis getTargetIRAnalysis() override;
const DataLayout *getDataLayout() const override { return &DL; }
const MipsSubtarget *getSubtargetImpl() const override {
if (Subtarget)
return Subtarget;

7
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -88,9 +88,10 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), is64bit(is64bit),
TLOF(make_unique<NVPTXTargetObjectFile>()),
DL(computeDataLayout(is64bit)), Subtarget(TT, CPU, FS, *this) {
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
CM, OL),
is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
if (Triple(TT).getOS() == Triple::NVCL)
drvInterface = NVPTX::NVCL;
else

2
lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@ -27,7 +27,6 @@ namespace llvm {
class NVPTXTargetMachine : public LLVMTargetMachine {
bool is64bit;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL; // Calculates type size & alignment
NVPTX::DrvInterface drvInterface;
NVPTXSubtarget Subtarget;
@ -40,7 +39,6 @@ public:
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
~NVPTXTargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
bool is64Bit() const { return is64bit; }
NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }

6
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -160,11 +160,11 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
CM, OL),
: LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
TargetABI(computeTargetABI(Triple(TT), Options)),
DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
Subtarget(TT, CPU, TargetFS, *this) {
initAsmInfo();
}

3
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -29,8 +29,6 @@ public:
private:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
PPCABI TargetABI;
// Calculates type size & alignment
const DataLayout DL;
PPCSubtarget Subtarget;
mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
@ -42,7 +40,6 @@ public:
~PPCTargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const PPCSubtarget *getSubtargetImpl(const Function &F) const override;

8
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -71,10 +71,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
DL(computeDataLayout(TT)),
TLOF(new TargetLoweringObjectFileELF()),
Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
OptLevel),
TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this),
IntrinsicInfo() {
setRequiresStructuredCFG(true);
initAsmInfo();
}

7
lib/Target/R600/AMDGPUTargetMachine.h
View File

@ -30,7 +30,6 @@ namespace llvm {
class AMDGPUTargetMachine : public LLVMTargetMachine {
private:
const DataLayout DL;
protected:
TargetLoweringObjectFile *TLOF;
@ -42,11 +41,7 @@ public:
StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine();
// FIXME: This is currently broken, the DataLayout needs to move to
// the target machine.
const DataLayout *getDataLayout() const override {
return &DL;
}
const AMDGPUSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

11
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -56,12 +56,11 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
DL(computeDataLayout(is64bit)),
Subtarget(TT, CPU, FS, *this, is64bit) {
CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo();
}

2
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -22,7 +22,6 @@ namespace llvm {
class SparcTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL;
SparcSubtarget Subtarget;
public:
SparcTargetMachine(const Target &T, StringRef TT,
@ -31,7 +30,6 @@ public:
CodeGenOpt::Level OL, bool is64bit);
~SparcTargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration

10
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -25,12 +25,12 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
// Make sure that global data has at least 16 bits of alignment by
// default, so that we can refer to it using LARL. We don't have any
// special requirements for stack variables though.
: LLVMTargetMachine(T, "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64",
TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
// Make sure that global data has at least 16 bits of alignment by
// default, so that we can refer to it using LARL. We don't have any
// special requirements for stack variables though.
DL("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

3
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -24,7 +24,6 @@ class TargetFrameLowering;
class SystemZTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL;
SystemZSubtarget Subtarget;
public:
@ -34,8 +33,6 @@ public:
CodeGenOpt::Level OL);
~SystemZTargetMachine() override;
// Override TargetMachine.
const DataLayout *getDataLayout() const override { return &DL; }
const SystemZSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}

10
lib/Target/TargetMachine.cpp
View File

@ -36,14 +36,12 @@ using namespace llvm;
// TargetMachine Class
//
TargetMachine::TargetMachine(const Target &T,
TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TT, StringRef CPU, StringRef FS,
const TargetOptions &Options)
: TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS),
CodeGenInfo(nullptr), AsmInfo(nullptr),
RequireStructuredCFG(false),
Options(Options) {
}
: TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
TargetFS(FS), CodeGenInfo(nullptr), AsmInfo(nullptr),
RequireStructuredCFG(false), Options(Options) {}
TargetMachine::~TargetMachine() {
delete CodeGenInfo;

4
lib/Target/X86/X86TargetMachine.cpp
View File

@ -94,9 +94,9 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
DL(computeDataLayout(Triple(TT))),
Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
// default to hard float ABI
if (Options.FloatABIType == FloatABI::Default)

3
lib/Target/X86/X86TargetMachine.h
View File

@ -24,8 +24,6 @@ class StringRef;
class X86TargetMachine final : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
// Calculates type size & alignment
const DataLayout DL;
X86Subtarget Subtarget;
mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
@ -35,7 +33,6 @@ public:
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
~X86TargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
const X86Subtarget *getSubtargetImpl(const Function &F) const override;

5
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -27,9 +27,10 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
: LLVMTargetMachine(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<XCoreTargetObjectFile>()),
DL("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32"),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

2
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -21,7 +21,6 @@ namespace llvm {
class XCoreTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
const DataLayout DL; // Calculates type size & alignment
XCoreSubtarget Subtarget;
public:
XCoreTargetMachine(const Target &T, StringRef TT,
@ -30,7 +29,6 @@ public:
CodeGenOpt::Level OL);
~XCoreTargetMachine() override;
const DataLayout *getDataLayout() const override { return &DL; }
const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration