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[X86] Encode the EVEX2VEX exception list information in .td files instead of the emitter source.
Rather than having an exclusion list in tablegen sources, add a flag to the X86 instruction records that can be used to suppress checking for convertibility. llvm-svn: 334971
This commit is contained in:
Craig Topper
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a174a3ecfa
commit
96f30be3bf
@ -4733,7 +4733,8 @@ defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
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defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
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SchedWriteVecIMul, HasBWI, 1>;
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defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
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SchedWriteVecIMul, HasDQI, 1>, T8PD;
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SchedWriteVecIMul, HasDQI, 1>, T8PD,
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NotEVEX2VEXConvertible;
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defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SchedWriteVecIMul,
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HasBWI, 1>;
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defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SchedWriteVecIMul,
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@ -4875,29 +4876,41 @@ defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
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SchedWriteVecALU, HasBWI, 1>, T8PD;
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defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
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SchedWriteVecALU, HasBWI, 1>;
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defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
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defm VPMAXSD : avx512_binop_rm_vl_d<0x3D, "vpmaxsd", smax,
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SchedWriteVecALU, HasAVX512, 1>, T8PD;
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defm VPMAXSQ : avx512_binop_rm_vl_q<0x3D, "vpmaxsq", smax,
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SchedWriteVecALU, HasAVX512, 1>, T8PD,
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NotEVEX2VEXConvertible;
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defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
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SchedWriteVecALU, HasBWI, 1>;
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defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
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SchedWriteVecALU, HasBWI, 1>, T8PD;
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defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
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defm VPMAXUD : avx512_binop_rm_vl_d<0x3F, "vpmaxud", umax,
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SchedWriteVecALU, HasAVX512, 1>, T8PD;
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defm VPMAXUQ : avx512_binop_rm_vl_q<0x3F, "vpmaxuq", umax,
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SchedWriteVecALU, HasAVX512, 1>, T8PD,
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NotEVEX2VEXConvertible;
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defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
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SchedWriteVecALU, HasBWI, 1>, T8PD;
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defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
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SchedWriteVecALU, HasBWI, 1>;
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defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
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defm VPMINSD : avx512_binop_rm_vl_d<0x39, "vpminsd", smin,
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SchedWriteVecALU, HasAVX512, 1>, T8PD;
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defm VPMINSQ : avx512_binop_rm_vl_q<0x39, "vpminsq", smin,
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SchedWriteVecALU, HasAVX512, 1>, T8PD,
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NotEVEX2VEXConvertible;
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defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
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SchedWriteVecALU, HasBWI, 1>;
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defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
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SchedWriteVecALU, HasBWI, 1>, T8PD;
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defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
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defm VPMINUD : avx512_binop_rm_vl_d<0x3B, "vpminud", umin,
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SchedWriteVecALU, HasAVX512, 1>, T8PD;
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defm VPMINUQ : avx512_binop_rm_vl_q<0x3B, "vpminuq", umin,
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SchedWriteVecALU, HasAVX512, 1>, T8PD,
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NotEVEX2VEXConvertible;
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// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX.
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let Predicates = [HasDQI, NoVLX] in {
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@ -5523,7 +5536,7 @@ multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr
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}
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}
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defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs,
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SchedWriteFAdd>, T8PD;
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SchedWriteFAdd>, T8PD, NotEVEX2VEXConvertible;
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//===----------------------------------------------------------------------===//
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// AVX-512 VPTESTM instructions
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@ -5765,9 +5778,11 @@ multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
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string OpcodeStr, SDNode OpNode,
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X86SchedWriteWidths sched> {
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X86SchedWriteWidths sched,
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bit NotEVEX2VEXConvertibleQ = 0> {
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defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, sched, v4i32,
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bc_v4i32, avx512vl_i32_info, HasAVX512>;
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let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in
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defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, sched, v2i64,
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bc_v2i64, avx512vl_i64_info, HasAVX512>, VEX_W;
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defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, sched, v8i16,
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@ -5812,9 +5827,11 @@ multiclass avx512_shift_rmi_w<bits<8> opcw, Format ImmFormR, Format ImmFormM,
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multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
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Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode,
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X86SchedWriteWidths sched> {
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X86SchedWriteWidths sched,
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bit NotEVEX2VEXConvertibleQ = 0> {
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defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
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sched, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
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let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in
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defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
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sched, avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
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}
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@ -5830,7 +5847,7 @@ defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli,
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SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V;
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defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai,
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SchedWriteVecShiftImm>,
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SchedWriteVecShiftImm, 1>,
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avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai,
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SchedWriteVecShiftImm>, AVX512BIi8Base, EVEX_4V;
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@ -5842,7 +5859,7 @@ defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli,
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defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl,
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SchedWriteVecShift>;
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defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra,
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SchedWriteVecShift>;
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SchedWriteVecShift, 1>;
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defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl,
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SchedWriteVecShift>;
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@ -7701,9 +7718,9 @@ multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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let Predicates = [HasDQI, HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode,
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sched.XMM>, EVEX_V128;
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sched.XMM>, EVEX_V128, NotEVEX2VEXConvertible;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode,
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sched.YMM>, EVEX_V256;
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sched.YMM>, EVEX_V256, NotEVEX2VEXConvertible;
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}
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}
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@ -7760,9 +7777,11 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode128,
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sched.XMM, "{1to2}", "{x}">, EVEX_V128;
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sched.XMM, "{1to2}", "{x}">, EVEX_V128,
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NotEVEX2VEXConvertible;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256;
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sched.YMM, "{1to4}", "{y}">, EVEX_V256,
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NotEVEX2VEXConvertible;
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def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
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@ -10263,7 +10282,7 @@ let Predicates = [HasVLX, HasBWI] in {
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defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw",
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SchedWritePSADBW, avx512vl_i16_info, avx512vl_i8_info>,
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EVEX_CD8<8, CD8VF>;
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EVEX_CD8<8, CD8VF>, NotEVEX2VEXConvertible;
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multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86FoldableSchedWrite sched, X86VectorVTInfo _> {
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@ -241,6 +241,9 @@ class FoldGenData<string _RegisterForm> {
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// Mark the instruction as "illegal to memory fold/unfold"
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class NotMemoryFoldable { bit isMemoryFoldable = 0; }
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// Prevent EVEX->VEX conversion from considering this instruction.
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class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr, Domain d = GenericDomain>
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: Instruction {
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@ -321,6 +324,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string FoldGenRegForm = ?;
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bit isMemoryFoldable = 1; // Is it allowed to memory fold/unfold this instruction?
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bit notEVEX2VEXConvertible = 0; // Prevent EVEX->VEX conversion.
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// TSFlags layout should be kept in sync with X86BaseInfo.h.
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let TSFlags{6-0} = FormBits;
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@ -52,35 +52,11 @@ private:
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// Prints the given table as a C++ array of type
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// X86EvexToVexCompressTableEntry
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void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
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bool inExceptionList(const CodeGenInstruction *Inst) {
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// List of EVEX instructions that match VEX instructions by the encoding
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// but do not perform the same operation.
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static constexpr const char *ExceptionList[] = {
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"VCVTQQ2PD",
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"VCVTQQ2PS",
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"VPMAXSQ",
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"VPMAXUQ",
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"VPMINSQ",
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"VPMINUQ",
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"VPMULLQ",
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"VPSRAQ",
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"VDBPSADBW",
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"VSCALEFPS"
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};
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// Instruction's name starts with one of the entries in the exception list
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for (StringRef InstStr : ExceptionList) {
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if (Inst->TheDef->getName().startswith(InstStr))
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return true;
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}
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return false;
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}
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};
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void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
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raw_ostream &OS) {
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std::string Size = (Table == EVEX2VEX128) ? "128" : "256";
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StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
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OS << "// X86 EVEX encoded instructions that have a VEX " << Size
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<< " encoding\n"
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@ -332,7 +308,7 @@ void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
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!Inst->TheDef->getValueAsBit("hasEVEX_B") &&
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getValueFromBitsInit(Inst->TheDef->
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getValueAsBitsInit("EVEX_LL")) != 2 &&
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!inExceptionList(Inst))
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!Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
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EVEXInsts.push_back(Inst);
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}
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