diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8b15727aaeb..321a9c360a5 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -161,8 +161,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
 
   if (X86ScalarSSE) {
     // Set up the FP register classes.
-    addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
-    addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
+    addRegisterClass(MVT::f32, X86::FR32RegisterClass);
+    addRegisterClass(MVT::f64, X86::FR64RegisterClass);
 
     // SSE has no load+extend ops
     setOperationAction(ISD::EXTLOAD,  MVT::f32, Expand);
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index d6dc20a7a8b..990faf677a2 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -74,7 +74,8 @@ def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov,
                         [SDNPOutFlag]>;
 def X86brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,
                         [SDNPHasChain]>;
-def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC,    []>;
+def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC,
+                        [SDNPOutFlag]>;
 
 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
                         [SDNPHasChain, SDNPOptInFlag]>;