From 9c179013501613c8bac25985da766f70ab17eb9d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 11 May 2019 05:18:58 +0000 Subject: [PATCH] [X86] Use getRegClassFor to simplify some code in fast isel. NFCI No need to select the register class based on type and features. It should already be setup by X86ISelLowering. llvm-svn: 360513 --- lib/Target/X86/X86FastISel.cpp | 58 +++++++++++----------------------- 1 file changed, 18 insertions(+), 40 deletions(-) diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 74464f28c02..1af68065c9e 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -84,7 +84,7 @@ private: bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT, const DebugLoc &DL); - bool X86FastEmitLoad(EVT VT, X86AddressMode &AM, MachineMemOperand *MMO, + bool X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg, unsigned Alignment = 1); bool X86FastEmitStore(EVT VT, const Value *Val, X86AddressMode &AM, @@ -314,7 +314,7 @@ bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. /// Return true and the result register by reference if it is possible. -bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, +bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg, unsigned Alignment) { bool HasSSE41 = Subtarget->hasSSE41(); @@ -324,46 +324,38 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, bool HasVLX = Subtarget->hasVLX(); bool IsNonTemporal = MMO && MMO->isNonTemporal(); + // Treat i1 loads the same as i8 loads. Masking will be done when storing. + if (VT == MVT::i1) + VT = MVT::i8; + // Get opcode and regclass of the output for the given load instruction. unsigned Opc = 0; - const TargetRegisterClass *RC = nullptr; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.SimpleTy) { default: return false; - case MVT::i1: case MVT::i8: Opc = X86::MOV8rm; - RC = &X86::GR8RegClass; break; case MVT::i16: Opc = X86::MOV16rm; - RC = &X86::GR16RegClass; break; case MVT::i32: Opc = X86::MOV32rm; - RC = &X86::GR32RegClass; break; case MVT::i64: // Must be in x86-64 mode. Opc = X86::MOV64rm; - RC = &X86::GR64RegClass; break; case MVT::f32: - if (X86ScalarSSEf32) { + if (X86ScalarSSEf32) Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm; - RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass; - } else { + else Opc = X86::LD_Fp32m; - RC = &X86::RFP32RegClass; - } break; case MVT::f64: - if (X86ScalarSSEf64) { + if (X86ScalarSSEf64) Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm; - RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass; - } else { + else Opc = X86::LD_Fp64m; - RC = &X86::RFP64RegClass; - } break; case MVT::f80: // No f80 support yet. @@ -378,7 +370,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, else Opc = HasVLX ? X86::VMOVUPSZ128rm : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm; - RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass; break; case MVT::v2f64: if (IsNonTemporal && Alignment >= 16 && HasSSE41) @@ -390,7 +381,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, else Opc = HasVLX ? X86::VMOVUPDZ128rm : HasAVX ? X86::VMOVUPDrm : X86::MOVUPDrm; - RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass; break; case MVT::v4i32: case MVT::v2i64: @@ -405,7 +395,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, else Opc = HasVLX ? X86::VMOVDQU64Z128rm : HasAVX ? X86::VMOVDQUrm : X86::MOVDQUrm; - RC = HasVLX ? &X86::VR128XRegClass : &X86::VR128RegClass; break; case MVT::v8f32: assert(HasAVX); @@ -417,7 +406,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm; else Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm; - RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass; break; case MVT::v4f64: assert(HasAVX); @@ -429,7 +417,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm; else Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm; - RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass; break; case MVT::v8i32: case MVT::v4i64: @@ -444,7 +431,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm; else Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm; - RC = HasVLX ? &X86::VR256XRegClass : &X86::VR256RegClass; break; case MVT::v16f32: assert(HasAVX512); @@ -452,7 +438,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = X86::VMOVNTDQAZrm; else Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm; - RC = &X86::VR512RegClass; break; case MVT::v8f64: assert(HasAVX512); @@ -460,7 +445,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = X86::VMOVNTDQAZrm; else Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm; - RC = &X86::VR512RegClass; break; case MVT::v8i64: case MVT::v16i32: @@ -473,10 +457,11 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, Opc = X86::VMOVNTDQAZrm; else Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; - RC = &X86::VR512RegClass; break; } + const TargetRegisterClass *RC = TLI.getRegClassFor(VT); + ResultReg = createResultReg(RC); MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); @@ -3754,26 +3739,19 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) { unsigned Opc = 0; bool HasAVX = Subtarget->hasAVX(); bool HasAVX512 = Subtarget->hasAVX512(); - const TargetRegisterClass *RC = nullptr; switch (VT.SimpleTy) { default: return 0; case MVT::f32: - if (X86ScalarSSEf32) { + if (X86ScalarSSEf32) Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm; - RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass; - } else { + else Opc = X86::LD_Fp32m; - RC = &X86::RFP32RegClass; - } break; case MVT::f64: - if (X86ScalarSSEf64) { + if (X86ScalarSSEf64) Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm; - RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass; - } else { + else Opc = X86::LD_Fp64m; - RC = &X86::RFP64RegClass; - } break; case MVT::f80: // No f80 support yet. @@ -3799,7 +3777,7 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) { // Create the load from the constant pool. unsigned CPI = MCP.getConstantPoolIndex(CFP, Align); - unsigned ResultReg = createResultReg(RC); + unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); if (CM == CodeModel::Large) { unsigned AddrReg = createResultReg(&X86::GR64RegClass);