diff --git a/lib/Target/SparcV8/InstSelectSimple.cpp b/lib/Target/SparcV8/InstSelectSimple.cpp
index 63d3dcc4904..95ff31ec75b 100644
--- a/lib/Target/SparcV8/InstSelectSimple.cpp
+++ b/lib/Target/SparcV8/InstSelectSimple.cpp
@@ -167,11 +167,27 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
                                     Constant *C, unsigned R) {
   if (C->getType()->isIntegral()) {
     unsigned Class = getClass(C->getType());
-
     ConstantInt *CI = cast<ConstantInt>(C);
-    // cByte: or %g0, <imm>, <dest>
-    // cShort or cInt: sethi, then or
-    // BuildMI(*MBB, IP, <opcode>, <#regs>, R).addImm(CI->getRawValue());
+    switch (Class) {
+      case cByte:
+        BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
+        return;
+      case cShort: {
+        unsigned TmpReg = makeAnotherReg (C->getType ());
+        BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
+        BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
+        return;
+      }
+      case cInt: {
+        unsigned TmpReg = makeAnotherReg (C->getType ());
+        BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
+        BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
+        return;
+      }
+      default:
+        assert (0 && "Can't move this kind of constant");
+        return;
+    }
   }
 
   assert (0 && "Can't copy constants into registers yet");
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 96e2dd19756..7a544047d42 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -62,9 +62,13 @@ def CALL : InstV8 {
   let Name = "call";
 }
 
+// Section B.9 - SETHI Instruction, p. 102
+def SETHIi: F2_1<0b100, "sethi">;
+
 // Section B.11 - Logical Instructions, p. 106
 def ANDri : F3_2<2, 0b000001, "and">;
 def ORrr  : F3_1<2, 0b000010, "or">;
+def ORri  : F3_2<2, 0b000010, "or">;
 
 // Section B.12 - Shift Instructions, p. 107
 def SLLri : F3_1<2, 0b100101, "sll">;