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ARM VSHR implied destination operand form aliases.
llvm-svn: 146192
This commit is contained in:
parent
d8a73b8918
commit
a33fa8aa88
lib/Target/ARM
test/MC/ARM
@ -201,21 +201,29 @@ def msr_mask : Operand<i32> {
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// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
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// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
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// 64 64 - <imm> is encoded in imm6<5:0>
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def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
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def shr_imm8 : Operand<i32> {
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let EncoderMethod = "getShiftRight8Imm";
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let DecoderMethod = "DecodeShiftRight8Imm";
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let ParserMatchClass = shr_imm8_asm_operand;
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}
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def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
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def shr_imm16 : Operand<i32> {
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let EncoderMethod = "getShiftRight16Imm";
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let DecoderMethod = "DecodeShiftRight16Imm";
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let ParserMatchClass = shr_imm16_asm_operand;
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}
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def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
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def shr_imm32 : Operand<i32> {
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let EncoderMethod = "getShiftRight32Imm";
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let DecoderMethod = "DecodeShiftRight32Imm";
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let ParserMatchClass = shr_imm32_asm_operand;
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}
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def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
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def shr_imm64 : Operand<i32> {
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let EncoderMethod = "getShiftRight64Imm";
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let DecoderMethod = "DecodeShiftRight64Imm";
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let ParserMatchClass = shr_imm64_asm_operand;
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}
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//===----------------------------------------------------------------------===//
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@ -5533,6 +5533,43 @@ def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
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def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
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(VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// VSHL (immediate) two-operand aliases.
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def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
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(VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
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(VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
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(VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
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(VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
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(VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
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(VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
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(VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
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(VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
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(VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
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(VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
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(VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
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(VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
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(VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
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(VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
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(VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
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(VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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// VLD1 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
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@ -643,6 +643,38 @@ public:
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int64_t Value = CE->getValue();
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return Value == 32;
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}
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bool isShrImm8() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value > 0 && Value <= 8;
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}
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bool isShrImm16() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value > 0 && Value <= 16;
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}
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bool isShrImm32() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value > 0 && Value <= 32;
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}
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bool isShrImm64() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value > 0 && Value <= 64;
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}
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bool isImm1_7() const {
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if (Kind != k_Immediate)
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return false;
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@ -70,6 +70,41 @@ _foo:
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@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2]
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@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2]
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@ implied destination operand variants.
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vshr.u8 d16, #7
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vshr.u16 d16, #15
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vshr.u32 d16, #31
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vshr.u64 d16, #63
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vshr.u8 q8, #7
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vshr.u16 q8, #15
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vshr.u32 q8, #31
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vshr.u64 q8, #63
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vshr.s8 d16, #7
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vshr.s16 d16, #15
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vshr.s32 d16, #31
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vshr.s64 d16, #63
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vshr.s8 q8, #7
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vshr.s16 q8, #15
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vshr.s32 q8, #31
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vshr.s64 q8, #63
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@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3]
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@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3]
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@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3]
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@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3]
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@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3]
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@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3]
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@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3]
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@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3]
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@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2]
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@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2]
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@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2]
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@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2]
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@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2]
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@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2]
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@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2]
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@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2]
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@ CHECK: vsra.u8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf3]
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vsra.u8 d16, d16, #7
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@ CHECK: vsra.u16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf3]
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