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Preliminary soft float support.
llvm-svn: 32394
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f1e9ec7225
commit
a366d082b5
@ -4351,9 +4351,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
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SDNode *Node = Op.Val;
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assert(getTypeAction(VT) == Expand && "Not an expanded type!");
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assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
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"Cannot expand FP values!");
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assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
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assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
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VT == MVT::Vector) &&
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"Cannot expand to FP value or to larger int value!");
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// See if we already expanded it.
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@ -4583,9 +4582,18 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
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}
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MVT::ValueType NVT = Node->getValueType(0);
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// f32 / f64 must be expanded to i32 / i64.
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if (NVT == MVT::f32 || NVT == MVT::f64) {
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Lo = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToTransformTo(NVT),
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Node->getOperand(0));
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Hi = DAG.getConstant(0, TLI.getTypeToTransformTo(NVT));
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break;
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}
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// Turn this into a load/store pair by default.
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if (Tmp.Val == 0)
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Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
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Tmp = ExpandBIT_CONVERT(NVT, Node->getOperand(0));
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ExpandOp(Tmp, Lo, Hi);
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break;
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@ -4858,6 +4866,25 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
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case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
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case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
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case ISD::FADD:
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Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node, Hi);
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break;
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case ISD::FSUB:
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Lo = ExpandLibCall(((VT == MVT::f32) ? "__subsf3" : "__subdf3"), Node, Hi);
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break;
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case ISD::FMUL:
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Lo = ExpandLibCall(((VT == MVT::f32) ? "__mulsf3" : "__muldf3"), Node, Hi);
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break;
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case ISD::FDIV:
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Lo = ExpandLibCall(((VT == MVT::f32) ? "__divsf3" : "__divdf3"), Node, Hi);
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break;
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case ISD::FP_EXTEND:
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Lo = ExpandLibCall("__extendsfdf2", Node, Hi);
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break;
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case ISD::FP_ROUND:
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Lo = ExpandLibCall("__truncdfsf2", Node, Hi);
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break;
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}
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// Make sure the resultant values have been legalized themselves, unless this
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@ -2954,7 +2954,10 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// integers it is.
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MVT::ValueType NVT = getTypeToTransformTo(VT);
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unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
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if (NumVals == 2) {
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if (NumVals == 1) {
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SDOperand Tmp = SDOperand(Result, i++);
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Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp));
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} else if (NumVals == 2) {
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SDOperand Lo = SDOperand(Result, i++);
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SDOperand Hi = SDOperand(Result, i++);
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@ -3040,7 +3043,10 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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// integers it is.
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MVT::ValueType NVT = getTypeToTransformTo(VT);
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unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
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if (NumVals == 2) {
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if (NumVals == 1) {
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Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, VT, Op));
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Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
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} else if (NumVals == 2) {
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
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DAG.getConstant(0, getPointerTy()));
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
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@ -3166,7 +3172,10 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
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} else {
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assert(MVT::isFloatingPoint(VT));
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ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
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if (getTypeAction(VT) == Expand)
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ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
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else
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ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
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}
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}
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} else if (RetTys.size() == 3) {
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@ -86,10 +86,17 @@ static void SetValueTypeAction(MVT::ValueType VT,
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assert(VT < PromoteTo && "Must promote to a larger type!");
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TransformToType[VT] = PromoteTo;
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} else if (Action == TargetLowering::Expand) {
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assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
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"Cannot expand this type: target must support SOME integer reg!");
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// Expand to the next smaller integer type!
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TransformToType[VT] = (MVT::ValueType)(VT-1);
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// f32 and f64 is each expanded to corresponding integer type of same size.
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if (VT == MVT::f32)
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TransformToType[VT] = MVT::i32;
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else if (VT == MVT::f64)
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TransformToType[VT] = MVT::i64;
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else {
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assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
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"Cannot expand this type: target must support SOME integer reg!");
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// Expand to the next smaller integer type!
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TransformToType[VT] = (MVT::ValueType)(VT-1);
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}
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}
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}
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@ -129,12 +136,27 @@ void TargetLowering::computeRegisterProperties() {
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else
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TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
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// If the target does not have native support for F32, promote it to F64.
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if (!isTypeLegal(MVT::f32))
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SetValueTypeAction(MVT::f32, Promote, *this,
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TransformToType, ValueTypeActions);
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else
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// If the target does not have native F64 support, expand it to I64. We will
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// be generating soft float library calls. If the target does not have native
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// support for F32, promote it to F64 if it is legal. Otherwise, expand it to
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// I32.
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if (isTypeLegal(MVT::f64))
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TransformToType[MVT::f64] = MVT::f64;
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else {
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NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
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SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
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ValueTypeActions);
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}
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if (isTypeLegal(MVT::f32))
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TransformToType[MVT::f32] = MVT::f32;
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else if (isTypeLegal(MVT::f64))
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SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
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ValueTypeActions);
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else {
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NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
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SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
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ValueTypeActions);
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}
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// Set MVT::Vector to always be Expanded
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SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
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@ -147,9 +169,6 @@ void TargetLowering::computeRegisterProperties() {
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if (isTypeLegal((MVT::ValueType)i))
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TransformToType[i] = (MVT::ValueType)i;
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}
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assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
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TransformToType[MVT::f64] = MVT::f64;
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}
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const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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