From a37c52f255476af611ef8e39a689cc5cf842afb1 Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Tue, 25 Nov 2008 00:23:16 +0000 Subject: [PATCH] CellSPU: Fix mnemonic typo in pattern; "shlqbyi" -> "shlqby". llvm-svn: 59998 --- lib/Target/CellSPU/SPUISelLowering.cpp | 2 ++ lib/Target/CellSPU/SPUInstrInfo.td | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 0b954743984..6e64caecb41 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -177,7 +177,9 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); +#if 0 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); +#endif // SPU has no intrinsics for these particular operations: setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 1d7800eafeb..227b6725517 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1982,7 +1982,7 @@ defm SHLQBII : ShiftLeftQuadByBitsImm; // not by bits. See notes above on SHLQBI. class SHLQBYInst pattern>: - RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB", + RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB", RotateShift, pattern>; class SHLQBYVecInst: