RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-29 14:20:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[TableGen] TypeSetByHwMode::operator== optimization

Browse Source 
This operator is called a great deal, by checking for the cheap isSimple equality cases first (a common occurrence) we can improve performance as we avoid a lot of std::map find/iteration in hasDefault.

isSimple also means that a default value is present, so we can avoid some hasDefault calls.

This also avoids a rather dodgy piece of logic that was checking for isSimple() && !VTS.isSimple() but not the inverse - it now uses the general hasDefault mode comparison test instead.

Saves around 15secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50841

llvm-svn: 339890
This commit is contained in:
Simon Pilgrim 2018-08-16 16:16:28 +00:00
parent cf78f22909
commit a4f9ec74a3
1 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
utils/TableGen/CodeGenDAGPatterns.cpp
View File

@ -198,15 +198,17 @@ void TypeSetByHwMode::writeToStream(const SetType &S, raw_ostream &OS) {
}
bool TypeSetByHwMode::operator==(const TypeSetByHwMode &VTS) const {
bool HaveDefault = hasDefault();
if (HaveDefault != VTS.hasDefault())
return false;
// The isSimple call is much quicker than hasDefault - check this first.
bool IsSimple = isSimple();
bool VTSIsSimple = VTS.isSimple();
if (IsSimple && VTSIsSimple)
return *begin() == *VTS.begin();
if (isSimple()) {
if (VTS.isSimple())
return *begin() == *VTS.begin();
// Speedup: We have a default if the set is simple.
bool HaveDefault = IsSimple || hasDefault();
bool VTSHaveDefault = VTSIsSimple || VTS.hasDefault();
if (HaveDefault != VTSHaveDefault)
return false;
}
SmallDenseSet<unsigned, 4> Modes;
for (auto &I : *this)