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[AVX512] Fix lowerV4X128VectorShuffle to select correctly input operands .

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Differential Revision: http://reviews.llvm.org/D19803

llvm-svn: 268368
This commit is contained in:
Igor Breger 2016-05-03 08:08:44 +00:00
parent 040f3d40e0
commit ab90b9e166
2 changed files with 50 additions and 4 deletions
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22
lib/Target/X86/X86ISelLowering.cpp
View File

@ -11542,6 +11542,23 @@ static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
if (!canWidenShuffleElements(Mask, WidenedMask))
return SDValue();
SDValue Ops[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT)};
// Insure elements came from the same Op.
int MaxOp1Index = VT.getVectorNumElements()/2 - 1;
for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
if (WidenedMask[i] == SM_SentinelZero)
return SDValue();
if (WidenedMask[i] == SM_SentinelUndef)
continue;
SDValue Op = WidenedMask[i] > MaxOp1Index ? V2 : V1;
unsigned OpIndex = (i < Size/2) ? 0 : 1;
if (Ops[OpIndex].isUndef())
Ops[OpIndex] = Op;
else if (Ops[OpIndex] != Op)
return SDValue();
}
// Form a 128-bit permutation.
// Convert the 64-bit shuffle mask selection values into 128-bit selection
// bits defined by a vshuf64x2 instruction's immediate control byte.
@ -11549,15 +11566,12 @@ static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
unsigned ControlBitsNum = WidenedMask.size() / 2;
for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
if (WidenedMask[i] == SM_SentinelZero)
return SDValue();
// Use first element in place of undef mask.
Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
}
return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
return DAG.getNode(X86ISD::SHUF128, DL, VT, Ops[0], Ops[1],
DAG.getConstant(PermMask, DL, MVT::i8));
}

32
test/CodeGen/X86/vector-shuffle-512-v8.ll
View File

@ -2271,3 +2271,35 @@ define <16 x float> @test_vshuff32x4_512(<16 x float> %x, <16 x float> %x1) noun
%res = shufflevector <16 x float> %x, <16 x float> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19>
ret <16 x float> %res
}
define <8 x double> @shuffle_v8f64_23014567(<8 x double> %a0, <8 x double> %a1) {
; ALL-LABEL: shuffle_v8f64_23014567:
; ALL: # BB#0:
; ALL-NEXT: vshuff64x2 $225, %zmm1, %zmm1, %zmm0 # zmm0 = zmm1[2,3,0,1,4,5,6,7]
%1 = shufflevector <8 x double> %a1, <8 x double> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %1
}
define <8 x double> @shuffle_v8f64_2301uu67(<8 x double> %a0, <8 x double> %a1) {
; ALL-LABEL: shuffle_v8f64_2301uu67:
; ALL: # BB#0:
; ALL-NEXT: vshuff64x2 $193, %zmm1, %zmm1, %zmm0 # zmm0 = zmm1[2,3,0,1,0,1,6,7]
%1 = shufflevector <8 x double> %a1, <8 x double> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 6, i32 7>
ret <8 x double> %1
}
define <8 x double> @shuffle_v8f64_2301uuuu(<8 x double> %a0, <8 x double> %a1) {
; ALL-LABEL: shuffle_v8f64_2301uuuu:
; ALL: # BB#0:
; ALL-NEXT: vshuff64x2 $1, %zmm0, %zmm1, %zmm0 # zmm0 = zmm1[2,3,0,1],zmm0[0,1,0,1]
%1 = shufflevector <8 x double> %a1, <8 x double> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x double> %1
}
define <8 x double> @shuffle_v8f64_uuu2301(<8 x double> %a0, <8 x double> %a1) {
; ALL-LABEL: shuffle_v8f64_uuu2301:
; ALL: # BB#0:
; ALL-NEXT: vshuff64x2 $16, %zmm1, %zmm0, %zmm0 # zmm0 = zmm0[0,1,0,1],zmm1[2,3,0,1]
%1 = shufflevector <8 x double> %a1, <8 x double> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 0, i32 1>
ret <8 x double> %1
}