From b3e0446dbb5fdcaff3da7e521a5e4d4c53500aee Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sat, 18 Jul 2009 13:33:17 +0000
Subject: [PATCH] Turn few asserts into errors / unreachable's

llvm-svn: 76313
---
 lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp |  4 ++--
 lib/Target/SystemZ/SystemZISelLowering.cpp          | 12 +++++++-----
 lib/Target/SystemZ/SystemZInstrInfo.cpp             | 10 +++++-----
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
index 24f4114ebc7..07c8ed0f82f 100644
--- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
+++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
@@ -183,7 +183,7 @@ void SystemZAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   if (printInstruction(MI))
     return;
 
-  assert(0 && "Should not happen");
+  llvm_unreachable("Unreachable!");
 }
 
 void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum) {
@@ -282,7 +282,7 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
 
   switch (MO.getTargetFlags()) {
   default:
-    assert(0 && "Unknown target flag on GV operand");
+    llvm_unreachable("Unknown target flag on GV operand");
   case SystemZII::MO_NO_FLAG:
     break;
   case SystemZII::MO_GOTENT:    O << "@GOTENT";    break;
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index b1d42cb18ad..10e969ddd67 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -161,7 +161,7 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
   case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
   case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
   default:
-    assert(0 && "unimplemented operand");
+    llvm_unreachable("Should not custom lower this!");
     return SDValue();
   }
 }
@@ -177,7 +177,7 @@ SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
   switch (CC) {
   default:
-    assert(0 && "Unsupported calling convention");
+    llvm_unreachable("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     return LowerCCCArguments(Op, DAG);
@@ -189,7 +189,7 @@ SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
   unsigned CallingConv = TheCall->getCallingConv();
   switch (CallingConv) {
   default:
-    assert(0 && "Unsupported calling convention");
+    llvm_unreachable("Unsupported calling convention");
   case CallingConv::Fast:
   case CallingConv::C:
     return LowerCCCCallTo(Op, DAG, CallingConv);
@@ -215,7 +215,8 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
 
-  assert(!isVarArg && "Varargs not supported yet");
+  if (isVarArg)
+    llvm_report_error("Varargs not supported yet");
 
   SmallVector<SDValue, 16> ArgValues;
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -534,7 +535,8 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
   bool isUnsigned = false;
   SystemZCC::CondCodes TCC;
   switch (CC) {
-  default: assert(0 && "Invalid integer condition!");
+  default:
+    llvm_unreachable("Invalid integer condition!");
   case ISD::SETEQ:
   case ISD::SETOEQ:
     TCC = SystemZCC::E;
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 27bd47dc08b..b7dfab5ea33 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -81,7 +81,7 @@ void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   } else if (RC == &SystemZ::GR128RegClass) {
     Opc = SystemZ::MOV128mr;
   } else
-    assert(0 && "Unsupported regclass to store");
+    llvm_unreachable("Unsupported regclass to store");
 
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
     .addReg(SrcReg, getKillRegState(isKill));
@@ -110,7 +110,7 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   } else if (RC == &SystemZ::GR128RegClass) {
     Opc = SystemZ::MOV128rm;
   } else
-    assert(0 && "Unsupported regclass to load");
+    llvm_unreachable("Unsupported regclass to load");
 
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
 }
@@ -584,7 +584,7 @@ const TargetInstrDesc&
 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
   switch (CC) {
   default:
-    assert(0 && "Unknown condition code!");
+   llvm_unreachable("Unknown condition code!");
   case SystemZCC::O:   return get(SystemZ::JO);
   case SystemZCC::H:   return get(SystemZ::JH);
   case SystemZCC::NLE: return get(SystemZ::JNLE);
@@ -627,7 +627,7 @@ SystemZCC::CondCodes
 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
   switch (CC) {
   default:
-   assert(0 && "Invalid condition!");
+    llvm_unreachable("Invalid condition!");
   case SystemZCC::O:   return SystemZCC::NO;
   case SystemZCC::H:   return SystemZCC::NH;
   case SystemZCC::NLE: return SystemZCC::LE;
@@ -649,7 +649,7 @@ const TargetInstrDesc&
 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
   switch (Opc) {
   default:
-   assert(0 && "Don't have long disp version of this instruction");
+    llvm_unreachable("Don't have long disp version of this instruction");
   case SystemZ::MOV32mr:   return get(SystemZ::MOV32mry);
   case SystemZ::MOV32rm:   return get(SystemZ::MOV32rmy);
   case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);