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[X86] When converting (x << C1) AND C2 to (x AND (C2>>C1)) << C1 during isel, try using andl over andq by favoring 32-bit unsigned immediates.

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llvm-svn: 357848
This commit is contained in:
Craig Topper 2019-04-06 19:00:11 +00:00
parent 9880ebc47c
commit b550b5787b
2 changed files with 14 additions and 7 deletions
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19
lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -3586,16 +3586,23 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
// Check the minimum bitwidth for the new constant.
// TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
auto CanShrinkImmediate = [&](int64_t &ShiftedVal) {
if (Opcode == ISD::AND) {
// AND32ri is the same as AND64ri32 with zext imm.
// Try this before sign extended immediates below.
ShiftedVal = (uint64_t)Val >> ShAmt;
if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
return true;
}
ShiftedVal = Val >> ShAmt;
if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) ||
(!isInt<32>(Val) && isInt<32>(ShiftedVal)))
return true;
// For 64-bit we can also try unsigned 32 bit immediates.
// AND32ri is the same as AND64ri32 with zext imm.
// MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
ShiftedVal = (uint64_t)Val >> ShAmt;
if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
return true;
if (Opcode != ISD::AND) {
// MOV32ri+OR64r/XOR64r is cheaper than MOV64ri64+OR64rr/XOR64rr
ShiftedVal = (uint64_t)Val >> ShAmt;
if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
return true;
}
return false;
};

2
test/CodeGen/X86/narrow-shl-cst.ll
View File

@ -66,7 +66,7 @@ define i64 @test6(i64 %x) nounwind {
; CHECK-LABEL: test6:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: andq $-65536, %rax # imm = 0xFFFF0000
; CHECK-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
; CHECK-NEXT: shlq $32, %rax
; CHECK-NEXT: retq
%and = shl i64 %x, 32