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Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
This commit is contained in:
Bruno Cardoso Lopes
parent
b98f50da03
commit
c0401dddf7
@ -11821,10 +11821,12 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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if (R.getNode())
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return R;
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// Want to form ANDNP nodes, in the hopes of then easily combining them with
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// OR and AND nodes to form PBLEND/PSIGN.
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// Want to form ANDNP nodes:
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// 1) In the hopes of then easily combining them with OR and AND nodes
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// to form PBLEND/PSIGN.
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// 2) To match ANDN packed intrinsics
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EVT VT = N->getValueType(0);
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if (VT != MVT::v2i64)
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if (VT != MVT::v2i64 && VT != MVT::v4i64)
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return SDValue();
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SDValue N0 = N->getOperand(0);
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@ -47,7 +47,7 @@ def X86pshufb : SDNode<"X86ISD::PSHUFB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86andnp : SDNode<"X86ISD::ANDNP",
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SDTypeProfile<1, 2, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignb : SDNode<"X86ISD::PSIGNB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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@ -1473,98 +1473,68 @@ let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
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///
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode, int HasPat = 0,
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list<list<dag>> Pattern = []> {
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SDNode OpNode> {
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let Pattern = []<dag> in {
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defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))]), 0>,
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VEX_4V;
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))], 0>, VEX_4V;
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defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))]), 0>,
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OpSize, VEX_4V;
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64 VR128:$src2))))],
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))], 0>,
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OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>, TB;
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))]>, TB;
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defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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TB, OpSize;
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64 VR128:$src2))))],
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))]>, TB, OpSize;
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}
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}
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/// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
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///
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multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
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SDNode OpNode, int HasNoPat = 0> {
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SDNode OpNode> {
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defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps"), f256mem,
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!if(HasNoPat, []<dag>, // rr
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1,
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VR256:$src2)))]),
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!if(HasNoPat, []<dag>, // rm
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[(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
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(memopv4i64 addr:$src2)))]), 0>, VEX_4V;
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>, VEX_4V;
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defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd"), f256mem,
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!if(HasNoPat, []<dag>, // rr
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(bc_v4i64 (v4f64 VR256:$src2))))]),
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!if(HasNoPat, []<dag>, // rm
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(memopv4i64 addr:$src2)))]), 0>,
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OpSize, VEX_4V;
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(bc_v4i64 (v4f64 VR256:$src2))))],
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[(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
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(memopv4i64 addr:$src2)))], 0>,
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OpSize, VEX_4V;
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}
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// AVX 256-bit packed logical ops forms
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defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
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defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
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defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
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let isCommutable = 0 in {
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defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", undef /* dummy */, 1>;
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}
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defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
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defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
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defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
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defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
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defm AND : sse12_fp_packed_logical<0x54, "and", and>;
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defm OR : sse12_fp_packed_logical<0x56, "or", or>;
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defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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let isCommutable = 0 in
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
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// single r+r
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[(set VR128:$dst, (X86andnp VR128:$src1, VR128:$src2))],
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// double r+r
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[],
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// single r+m
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[(set VR128:$dst, (X86andnp VR128:$src1, (memopv2i64 addr:$src2)))],
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// double r+m
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[]]>;
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Arithmetic Instructions
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@ -3678,6 +3648,7 @@ let Predicates = [HasAVX] in {
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def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
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def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
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def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
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def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
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}
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// Move scalar to XMM zero-extended
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@ -114,3 +114,48 @@ entry:
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ret <8 x float> %1
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}
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; CHECK: vandnpd
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define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp {
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entry:
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%0 = bitcast <4 x double> %x to <4 x i64>
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%neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
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%1 = bitcast <4 x double> %y to <4 x i64>
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%and.i = and <4 x i64> %1, %neg.i
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%2 = bitcast <4 x i64> %and.i to <4 x double>
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ret <4 x double> %2
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}
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; CHECK: vandnpd (%
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define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp {
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entry:
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%tmp2 = load <4 x double>* %x, align 32
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%0 = bitcast <4 x double> %y to <4 x i64>
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%neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1>
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%1 = bitcast <4 x double> %tmp2 to <4 x i64>
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%and.i = and <4 x i64> %1, %neg.i
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%2 = bitcast <4 x i64> %and.i to <4 x double>
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ret <4 x double> %2
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}
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; CHECK: vandnps
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define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp {
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entry:
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%0 = bitcast <8 x float> %x to <8 x i32>
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%neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = bitcast <8 x float> %y to <8 x i32>
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%and.i = and <8 x i32> %1, %neg.i
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%2 = bitcast <8 x i32> %and.i to <8 x float>
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ret <8 x float> %2
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}
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; CHECK: vandnps (%
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define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp {
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entry:
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%tmp2 = load <8 x float>* %x, align 32
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%0 = bitcast <8 x float> %y to <8 x i32>
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%neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = bitcast <8 x float> %tmp2 to <8 x i32>
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%and.i = and <8 x i32> %1, %neg.i
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%2 = bitcast <8 x i32> %and.i to <8 x float>
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ret <8 x float> %2
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}
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