From c754478fbeef1a030498cdb2fc8edaf674d6134c Mon Sep 17 00:00:00 2001
From: Duraid Madina <duraid@octopus.com.au>
Date: Tue, 1 Nov 2005 03:07:25 +0000
Subject: [PATCH] add support for int->FP and FP->int ops, and add ia64
 patterns for these

llvm-svn: 24132
---
 lib/Target/IA64/IA64InstrInfo.td | 12 ++++++++++++
 lib/Target/TargetSelectionDAG.td | 11 +++++++++++
 2 files changed, 23 insertions(+)

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 13443c3d22f..0ec4022f513 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -553,6 +553,18 @@ def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
   "setf.sig $dst = $src;;">;
 
+// these four FP<->int conversion patterns need checking/cleaning
+def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
+  (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
+def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
+  (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
+/* FIXME: tablegen coughs on these
+def FP_TO_SINT : Pat<(fp_to_sint FP:$src),
+  (GETFSIG (FCVTFXTRUNC FP:$src))>;
+def FP_TO_UINT : Pat<(fp_to_uint FP:$src),
+  (GETFSIG (FCVTFXUTRUNC FP:$src))>;
+*/
+
 let isTerminator = 1, isBranch = 1 in {
   def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
     "(p0) brl.cond.sptk $dst;;">;
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index f58d4ab7145..f492ab38d48 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -94,6 +94,12 @@ def SDTFPRoundOp  : SDTypeProfile<1, 1, [   // fround
 def SDTFPExtendOp  : SDTypeProfile<1, 1, [   // fextend
   SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
 ]>;
+def SDTIntToFPOp : SDTypeProfile<1, 1, [   // [su]int_to_fp 
+  SDTCisFP<0>, SDTCisInt<1>
+]>;
+def SDTFPToIntOp : SDTypeProfile<1, 1, [   // fp_to_[su]int 
+  SDTCisInt<0>, SDTCisFP<1>
+]>;
 def SDTExtInreg : SDTypeProfile<1, 2, [   // sext_inreg
   SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
   SDTCisVTSmallerThanOp<2, 1>
@@ -172,6 +178,11 @@ def fsqrt      : SDNode<"ISD::FSQRT"      , SDTFPUnaryOp>;
 def fround     : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fextend    : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
 
+def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
+def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
+def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
+def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
+
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 
 //===----------------------------------------------------------------------===//