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Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135319
This commit is contained in:
Owen Anderson
parent
a44add3a49
commit
cd207640a2
@ -390,8 +390,8 @@ let isCall = 1,
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Uses = [SP] in {
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// Also used for Thumb2
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def tBL : TIx2<0b11110, 0b11, 1,
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(outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
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"bl\t$func",
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(outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
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"bl${p}\t$func",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb, IsNotDarwin]> {
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bits<21> func;
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@ -403,8 +403,8 @@ let isCall = 1,
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// ARMv5T and above, also used for Thumb2
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def tBLXi : TIx2<0b11110, 0b11, 0,
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(outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
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"blx\t$func",
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(outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
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"blx${p}\t$func",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]> {
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bits<21> func;
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@ -416,8 +416,8 @@ let isCall = 1,
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}
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// Also used for Thumb2
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def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
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"blx\t$func",
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def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
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"blx${p}\t$func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]>,
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T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
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@ -440,43 +440,22 @@ let isCall = 1,
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Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
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Uses = [R7, SP] in {
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// Also used for Thumb2
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def tBLr9 : TIx2<0b11110, 0b11, 1,
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(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
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IIC_Br, "bl${p}\t$func",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb, IsDarwin]> {
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bits<21> func;
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let Inst{25-16} = func{20-11};
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let Inst{13} = 1;
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let Inst{11} = 1;
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let Inst{10-0} = func{10-0};
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}
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def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
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4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
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(tBL pred:$p, t_bltarget:$func)>,
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Requires<[IsThumb, IsDarwin]>;
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// ARMv5T and above, also used for Thumb2
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def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
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(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
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IIC_Br, "blx${p}\t$func",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T, IsDarwin]> {
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bits<21> func;
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let Inst{25-16} = func{20-11};
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let Inst{13} = 1;
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let Inst{11} = 1;
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let Inst{10-1} = func{10-1};
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let Inst{0} = 0; // func{0} is assumed zero
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}
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def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
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4, IIC_Br, [(ARMcall tglobaladdr:$func)],
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(tBLXi pred:$p, t_blxtarget:$func)>,
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Requires<[IsThumb, HasV5T, IsDarwin]>;
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// Also used for Thumb2
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def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
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"blx${p}\t$func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T, IsDarwin]>,
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T1Special<{1,1,1,?}> {
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// A6.2.3 & A8.6.24
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bits<4> func;
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let Inst{6-3} = func;
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let Inst{2-0} = 0b000;
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}
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def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
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2, IIC_Br, [(ARMtcall GPR:$func)],
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(tBLXr pred:$p, GPR:$func)>,
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Requires<[IsThumb, HasV5T, IsDarwin]>;
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// ARMv4T
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def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
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@ -498,8 +477,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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// Just a pseudo for a tBL instruction. Needed to let regalloc know about
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// the clobber of LR.
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let Defs = [LR] in
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def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target),
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4, IIC_Br, [], (tBL t_bltarget:$target)>;
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def tBfar : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$target),
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4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
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def tBR_JTr : tPseudoInst<(outs),
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(ins tGPR:$target, i32imm:$jt, i32imm:$id),
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@ -479,7 +479,7 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
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// tBX: Rm
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// tBX_RET: 0 operand
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// tBX_RET_vararg: Rm
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// tBLXr_r9: Rm
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// tBLXr: Rm
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// tBRIND: Rm
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static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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@ -489,8 +489,8 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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return true;
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// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
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if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
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if (Opcode == ARM::tBLXr_r9) {
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if (Opcode==ARM::tBLXr || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
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if (Opcode == ARM::tBLXr) {
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// Handling the two predicate operands before the reg operand.
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if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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return false;
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@ -1729,7 +1729,7 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) {
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// Branches: t2TPsoft -> no operand
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//
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// A8.6.23 BL, BLX (immediate)
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// Branches (defined in ARMInstrThumb.td): tBLr9, tBLXi_r9 -> imm operand
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// Branches (defined in ARMInstrThumb.td): tBL, tBLXi -> imm operand
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//
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// A8.6.26
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// t2BXJ -> Rn
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@ -1844,7 +1844,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
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}
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// Some instructions have predicate operands first before the immediate.
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if (Opcode == ARM::tBLXi_r9 || Opcode == ARM::tBLr9) {
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if (Opcode == ARM::tBLXi || Opcode == ARM::tBL) {
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// Handling the two predicate operands before the imm operand.
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if (B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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NumOpsAdded += 2;
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@ -1867,10 +1867,10 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
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case ARM::t2Bcc:
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Offset = decodeImm32_B_EncodingT3(insn);
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break;
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case ARM::tBLr9:
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case ARM::tBL:
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Offset = decodeImm32_BL(insn);
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break;
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case ARM::tBLXi_r9:
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case ARM::tBLXi:
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Offset = decodeImm32_BLX(insn);
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break;
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}
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@ -1619,10 +1619,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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if (Name == "tSTMIA")
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return false;
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// On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts.
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if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
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return false;
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// A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg.
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if (Name == "tBX_RET" || Name == "tBX_RET_vararg")
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return false;
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@ -1654,14 +1650,12 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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// Resolve conflicts:
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//
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// tBfar conflicts with tBLr9
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// t2LDMIA_RET conflict with t2LDM (ditto)
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// tMOVCCi conflicts with tMOVi8
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// tMOVCCr conflicts with tMOVgpr2gpr
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// tLDRcp conflicts with tLDRspi
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// t2MOVCCi16 conflicts with tMOVi16
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if (Name == "tBfar" ||
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Name == "t2LDMIA_RET" ||
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if (Name == "t2LDMIA_RET" ||
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Name == "tMOVCCi" || Name == "tMOVCCr" ||
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Name == "tLDRcp" ||
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Name == "t2MOVCCi16")
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