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R600: Use DAG lowering pass to handle fcos/fsin
NOTE: This is a candidate for the stable branch. llvm-svn: 185940
This commit is contained in:
Vincent Lejeune
parent
4c202a6875
commit
d29844ad2e
@ -121,6 +121,8 @@ enum {
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// End AMDIL ISD Opcodes
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DWORDADDR,
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FRACT,
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COS_HW,
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SIN_HW,
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FMAX,
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SMAX,
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UMAX,
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@ -26,7 +26,8 @@
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using namespace llvm;
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R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM) {
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AMDGPUTargetLowering(TM),
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Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
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addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
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@ -38,6 +39,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
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setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Custom);
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setOperationAction(ISD::FSIN, MVT::f32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
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@ -473,6 +477,8 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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switch (Op.getOpcode()) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case ISD::FCOS:
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case ISD::FSIN: return LowerTrig(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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@ -723,6 +729,37 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
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}
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}
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SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
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// On hw >= R700, COS/SIN input must be between -1. and 1.
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// Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
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EVT VT = Op.getValueType();
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SDValue Arg = Op.getOperand(0);
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SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
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DAG.getNode(ISD::FADD, SDLoc(Op), VT,
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DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
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DAG.getConstantFP(0.15915494309, MVT::f32)),
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DAG.getConstantFP(0.5, MVT::f32)));
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unsigned TrigNode;
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switch (Op.getOpcode()) {
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case ISD::FCOS:
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TrigNode = AMDGPUISD::COS_HW;
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break;
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case ISD::FSIN:
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TrigNode = AMDGPUISD::SIN_HW;
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break;
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default:
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llvm_unreachable("Wrong trig opcode");
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}
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SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
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DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
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DAG.getConstantFP(-0.5, MVT::f32)));
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if (Gen >= AMDGPUSubtarget::R700)
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return TrigVal;
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// On R600 hw, COS/SIN input must be between -Pi and Pi.
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return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
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DAG.getConstantFP(3.14159265359, MVT::f32));
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}
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SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(
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ISD::SETCC,
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@ -40,6 +40,7 @@ public:
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SmallVectorImpl<SDValue> &InVals) const;
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virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
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private:
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unsigned Gen;
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/// Each OpenCL kernel has nine implicit parameters that are stored in the
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/// first nine dwords of a Vertex Buffer. These implicit parameters are
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/// lowered to load instructions which retreive the values from the Vertex
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@ -60,6 +61,7 @@ private:
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SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
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SelectionDAG &DAG) const;
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@ -364,6 +364,14 @@ def DOT4 : SDNode<"AMDGPUISD::DOT4",
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[]
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>;
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def COS_HW : SDNode<"AMDGPUISD::COS_HW",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
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>;
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def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
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>;
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def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
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def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
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@ -1080,14 +1088,14 @@ class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
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}
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class SIN_Common <bits<11> inst> : R600_1OP <
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inst, "SIN", []>{
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inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
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let Trig = 1;
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let TransOnly = 1;
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let Itinerary = TransALU;
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}
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class COS_Common <bits<11> inst> : R600_1OP <
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inst, "COS", []> {
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inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
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let Trig = 1;
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let TransOnly = 1;
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let Itinerary = TransALU;
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@ -1228,18 +1236,6 @@ let Predicates = [isR600] in {
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}
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// Helper pattern for normalizing inputs to triginomic instructions for R700+
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// cards.
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class COS_PAT <InstR600 trig> : Pat<
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(fcos f32:$src),
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(trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
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>;
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class SIN_PAT <InstR600 trig> : Pat<
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(fsin f32:$src),
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(trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
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>;
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//===----------------------------------------------------------------------===//
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// R700 Only instructions
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//===----------------------------------------------------------------------===//
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@ -1247,10 +1243,6 @@ class SIN_PAT <InstR600 trig> : Pat<
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let Predicates = [isR700] in {
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def SIN_r700 : SIN_Common<0x6E>;
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def COS_r700 : COS_Common<0x6F>;
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// R700 normalizes inputs to SIN/COS the same as EG
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def : SIN_PAT <SIN_r700>;
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def : COS_PAT <COS_r700>;
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}
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//===----------------------------------------------------------------------===//
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@ -1276,8 +1268,6 @@ def SIN_eg : SIN_Common<0x8D>;
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def COS_eg : COS_Common<0x8E>;
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def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
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def : SIN_PAT <SIN_eg>;
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def : COS_PAT <COS_eg>;
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def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
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//===----------------------------------------------------------------------===//
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@ -1726,8 +1716,6 @@ def COS_cm : COS_Common<0x8E>;
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} // End isVector = 1
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def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
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def : SIN_PAT <SIN_cm>;
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def : COS_PAT <COS_cm>;
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defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
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@ -1,5 +1,8 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: MULADD_IEEE *
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;CHECK: FRACT *
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;CHECK: ADD *
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;CHECK: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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define void @test() {
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@ -1,5 +1,8 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: MULADD_IEEE *
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;CHECK: FRACT *
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;CHECK: ADD *
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;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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define void @test() {
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