diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index 0a29f9e8f41..62e993581ad 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -266,6 +266,15 @@ names from both the *Processor* and *Alternative Processor* can be used. .. TODO Add product names. + ``gfx1031`` ``amdgcn`` dGPU - xnack *TBA* + [off] + - wavefrontsize64 + [off] + - cumode + [off] + .. TODO + Add product + names. =========== =============== ============ ===== ================= ======= ====================== .. _amdgpu-target-features: @@ -810,6 +819,7 @@ The AMDGPU backend uses the following ELF header: ``EF_AMDGPU_MACH_AMDGCN_GFX1011`` 0x034 ``gfx1011`` ``EF_AMDGPU_MACH_AMDGCN_GFX1012`` 0x035 ``gfx1012`` ``EF_AMDGPU_MACH_AMDGCN_GFX1030`` 0x036 ``gfx1030`` + ``EF_AMDGPU_MACH_AMDGCN_GFX1031`` 0x037 ``gfx1031`` ================================= ========== ============================= Sections diff --git a/include/llvm/BinaryFormat/ELF.h b/include/llvm/BinaryFormat/ELF.h index bdcf10fd164..a1eb4d0383f 100644 --- a/include/llvm/BinaryFormat/ELF.h +++ b/include/llvm/BinaryFormat/ELF.h @@ -707,6 +707,7 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX1011 = 0x034, EF_AMDGPU_MACH_AMDGCN_GFX1012 = 0x035, EF_AMDGPU_MACH_AMDGCN_GFX1030 = 0x036, + EF_AMDGPU_MACH_AMDGCN_GFX1031 = 0x037, // Reserved for AMDGCN-based processors. EF_AMDGPU_MACH_AMDGCN_RESERVED0 = 0x027, @@ -714,7 +715,7 @@ enum : unsigned { // First/last AMDGCN-based processors. EF_AMDGPU_MACH_AMDGCN_FIRST = EF_AMDGPU_MACH_AMDGCN_GFX600, - EF_AMDGPU_MACH_AMDGCN_LAST = EF_AMDGPU_MACH_AMDGCN_GFX1030, + EF_AMDGPU_MACH_AMDGCN_LAST = EF_AMDGPU_MACH_AMDGCN_GFX1031, // Indicates if the "xnack" target feature is enabled for all code contained // in the object. diff --git a/include/llvm/Support/TargetParser.h b/include/llvm/Support/TargetParser.h index f521d8f836b..f909729b407 100644 --- a/include/llvm/Support/TargetParser.h +++ b/include/llvm/Support/TargetParser.h @@ -85,9 +85,10 @@ enum GPUKind : uint32_t { GK_GFX1011 = 72, GK_GFX1012 = 73, GK_GFX1030 = 75, + GK_GFX1031 = 76, GK_AMDGCN_FIRST = GK_GFX600, - GK_AMDGCN_LAST = GK_GFX1030, + GK_AMDGCN_LAST = GK_GFX1031, }; /// Instruction set architecture version. diff --git a/lib/ObjectYAML/ELFYAML.cpp b/lib/ObjectYAML/ELFYAML.cpp index f460a387540..319e37022c8 100644 --- a/lib/ObjectYAML/ELFYAML.cpp +++ b/lib/ObjectYAML/ELFYAML.cpp @@ -430,6 +430,7 @@ void ScalarBitSetTraits::bitset(IO &IO, BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1011, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1012, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1030, EF_AMDGPU_MACH); + BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1031, EF_AMDGPU_MACH); BCase(EF_AMDGPU_XNACK); BCase(EF_AMDGPU_SRAM_ECC); break; diff --git a/lib/Support/TargetParser.cpp b/lib/Support/TargetParser.cpp index 031384ebaa9..7adfd806ee6 100644 --- a/lib/Support/TargetParser.cpp +++ b/lib/Support/TargetParser.cpp @@ -63,7 +63,7 @@ constexpr GPUInfo R600GPUs[26] = { // This table should be sorted by the value of GPUKind // Don't bother listing the implicitly true features -constexpr GPUInfo AMDGCNGPUs[38] = { +constexpr GPUInfo AMDGCNGPUs[39] = { // Name Canonical Kind Features // Name {{"gfx600"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32}, @@ -104,6 +104,7 @@ constexpr GPUInfo AMDGCNGPUs[38] = { {{"gfx1011"}, {"gfx1011"}, GK_GFX1011, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, {{"gfx1012"}, {"gfx1012"}, GK_GFX1012, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, {{"gfx1030"}, {"gfx1030"}, GK_GFX1030, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, + {{"gfx1031"}, {"gfx1031"}, GK_GFX1031, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, }; const GPUInfo *getArchEntry(AMDGPU::GPUKind AK, ArrayRef Table) { @@ -206,6 +207,7 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { case GK_GFX1011: return {10, 1, 1}; case GK_GFX1012: return {10, 1, 2}; case GK_GFX1030: return {10, 3, 0}; + case GK_GFX1031: return {10, 3, 1}; default: return {0, 0, 0}; } } diff --git a/lib/Target/AMDGPU/GCNProcessors.td b/lib/Target/AMDGPU/GCNProcessors.td index 17e6098d880..8b0132a5596 100644 --- a/lib/Target/AMDGPU/GCNProcessors.td +++ b/lib/Target/AMDGPU/GCNProcessors.td @@ -187,3 +187,7 @@ def : ProcessorModel<"gfx1012", GFX10SpeedModel, def : ProcessorModel<"gfx1030", GFX10SpeedModel, FeatureISAVersion10_3_0.Features >; + +def : ProcessorModel<"gfx1031", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features +>; diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index 3d202d7960d..d040efe878b 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -98,6 +98,7 @@ StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; } @@ -150,6 +151,7 @@ unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; + case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; } diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir index 4a72033af51..97cc62e20ba 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir @@ -3,6 +3,7 @@ # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX101 %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX103 %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1031 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX103 %s --- name: test_fmad_s32_flush diff --git a/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll b/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll index 9bc56d124a9..8eee8a80eb8 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN define i32 @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) { ; GCN-LABEL: global_atomic_csub: diff --git a/test/CodeGen/AMDGPU/elf-header-flags-mach.ll b/test/CodeGen/AMDGPU/elf-header-flags-mach.ll index 8679e4e4853..15c8ca8a279 100644 --- a/test/CodeGen/AMDGPU/elf-header-flags-mach.ll +++ b/test/CodeGen/AMDGPU/elf-header-flags-mach.ll @@ -52,6 +52,7 @@ ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1011 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1011 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1012 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1012 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1030 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1030 %s +; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1031 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1031 %s ; ARCH-R600: Arch: r600 ; ARCH-GCN: Arch: amdgcn @@ -98,6 +99,7 @@ ; GFX1011: EF_AMDGPU_MACH_AMDGCN_GFX1011 (0x34) ; GFX1012: EF_AMDGPU_MACH_AMDGCN_GFX1012 (0x35) ; GFX1030: EF_AMDGPU_MACH_AMDGCN_GFX1030 (0x36) +; GFX1031: EF_AMDGPU_MACH_AMDGCN_GFX1031 (0x37) ; ALL: ] define amdgpu_kernel void @elf_header() { diff --git a/test/CodeGen/AMDGPU/hsa-note-no-func.ll b/test/CodeGen/AMDGPU/hsa-note-no-func.ll index 6b4c7309e15..071180660ac 100644 --- a/test/CodeGen/AMDGPU/hsa-note-no-func.ll +++ b/test/CodeGen/AMDGPU/hsa-note-no-func.ll @@ -29,6 +29,7 @@ ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1011 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1011 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1012 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1012 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1030 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1031 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1031 %s ; HSA: .hsa_code_object_version 2,1 ; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU" @@ -52,3 +53,4 @@ ; HSA-GFX1011: .hsa_code_object_isa 10,1,1,"AMD","AMDGPU" ; HSA-GFX1012: .hsa_code_object_isa 10,1,2,"AMD","AMDGPU" ; HSA-GFX1030: .hsa_code_object_isa 10,3,0,"AMD","AMDGPU" +; HSA-GFX1031: .hsa_code_object_isa 10,3,1,"AMD","AMDGPU" diff --git a/test/CodeGen/AMDGPU/idot8s.ll b/test/CodeGen/AMDGPU/idot8s.ll index e7d48de6ed6..fbc602b3a92 100644 --- a/test/CodeGen/AMDGPU/idot8s.ll +++ b/test/CodeGen/AMDGPU/idot8s.ll @@ -6,6 +6,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s define amdgpu_kernel void @idot8_acc32(<8 x i4> addrspace(1)* %src1, ; GFX7-LABEL: idot8_acc32: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll index e3fd229f77b..4ab8c344658 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s -check-prefix=GCN +; RUN: llc < %s -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs | FileCheck %s -check-prefix=GCN declare i32 @llvm.amdgcn.buffer.atomic.csub(i32, <4 x i32>, i32, i32, i1) declare i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)*, i32) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll index 0fa11c4646e..41661015f90 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll @@ -2,6 +2,7 @@ ; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 ; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 +; RUN: llc -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 %clamp) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll index 3d87ad05d4f..948bc530c03 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll @@ -3,6 +3,7 @@ ; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 ; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 +; RUN: llc -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10 declare i32 @llvm.amdgcn.sdot8(i32 %a, i32 %b, i32 %c, i1 %clamp) diff --git a/test/MC/AMDGPU/gfx1030_err.s b/test/MC/AMDGPU/gfx1030_err.s index 804e4b8b5b7..29d906ec838 100644 --- a/test/MC/AMDGPU/gfx1030_err.s +++ b/test/MC/AMDGPU/gfx1030_err.s @@ -1,4 +1,5 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX10 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1031 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX10 %s v_dot8c_i32_i4 v5, v1, v2 // GFX10: error: diff --git a/test/MC/AMDGPU/gfx1030_new.s b/test/MC/AMDGPU/gfx1030_new.s index 5f6aea871b3..7125fd2782a 100644 --- a/test/MC/AMDGPU/gfx1030_new.s +++ b/test/MC/AMDGPU/gfx1030_new.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s global_load_dword_addtid v1, s[2:3] offset:16 // GFX10: encoding: [0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01] diff --git a/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt b/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt index eb9b7e2219d..ba4348bfa9f 100644 --- a/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt +++ b/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s # GFX10: global_load_dword_addtid v1, s[2:3] offset:16 0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01 diff --git a/tools/llvm-readobj/ELFDumper.cpp b/tools/llvm-readobj/ELFDumper.cpp index 54b2d67421d..aca33858c6c 100644 --- a/tools/llvm-readobj/ELFDumper.cpp +++ b/tools/llvm-readobj/ELFDumper.cpp @@ -1841,6 +1841,7 @@ static const EnumEntry ElfHeaderAMDGPUFlags[] = { LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1012), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1030), + LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1031), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_XNACK), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_SRAM_ECC) };