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Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
llvm-svn: 133289
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@ -3017,6 +3017,12 @@ def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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(and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsARM, HasV6]>;
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def : ARMV6Pat<(or (or (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl GPR:$Rm, (i32 8)), 0xFF000000)),
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(and (srl GPR:$Rm, (i32 8)), 0xFF)),
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(and (shl GPR:$Rm, (i32 8)), 0xFF00)),
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(REV16 GPR:$Rm)>;
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def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "revsh", "\t$Rd, $Rm",
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[(set GPR:$Rd,
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@ -2593,6 +2593,12 @@ def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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(or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
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def : T2Pat<(or (or (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl rGPR:$Rm, (i32 8)), 0xFF000000)),
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(and (srl rGPR:$Rm, (i32 8)), 0xFF)),
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(and (shl rGPR:$Rm, (i32 8)), 0xFF00)),
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(t2REV16 rGPR:$Rm)>;
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def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"revsh", ".w\t$Rd, $Rm",
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[(set rGPR:$Rd,
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@ -67,3 +67,20 @@ entry:
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%or = or i32 %shr, %and
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ret i32 %or
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}
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; rdar://9609108
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define i32 @test6(i32 %x) nounwind readnone {
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entry:
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; CHECK: test6
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; CHECK: rev16 r0, r0
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%and = shl i32 %x, 8
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%shl = and i32 %and, 65280
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%and2 = lshr i32 %x, 8
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%shr11 = and i32 %and2, 255
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%shr5 = and i32 %and2, 16711680
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%shl9 = and i32 %and, -16777216
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%or = or i32 %shr5, %shl9
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%or6 = or i32 %or, %shr11
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%or10 = or i32 %or6, %shl
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ret i32 %or10
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}
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