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Switch Alpha over to the new call lowering style. New code mostly
copied from the SystemZ target. I don't think this causes any significant changes to the output (I compared the assembly, and the results appeared to be essentially unchanged), although I don't actually have an Alpha to test on. I would appreciate if anyone with the appropriate hardware could test this. I'm not sure if that includes anyone subscribed to llvm-commits, though. llvm-svn: 76353
This commit is contained in:
Eli Friedman
parent
e52f9f19ff
commit
e208ce316a
@ -29,6 +29,12 @@ def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
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include "AlphaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling Convention Description
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//===----------------------------------------------------------------------===//
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include "AlphaCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Schedule Description
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//===----------------------------------------------------------------------===//
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37
lib/Target/Alpha/AlphaCallingConv.td
Normal file
37
lib/Target/Alpha/AlphaCallingConv.td
Normal file
@ -0,0 +1,37 @@
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//===- AlphaCallingConv.td - Calling Conventions for Alpha -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for Alpha architecture.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Alpha Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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def RetCC_Alpha : CallingConv<[
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// i64 is returned in register R0
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CCIfType<[i64], CCAssignToReg<[R0]>>,
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// f32 / f64 are returned in F0/F1
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CCIfType<[f32, f64], CCAssignToReg<[F0, F1]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Alpha Argument Calling Conventions
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//===----------------------------------------------------------------------===//
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def CC_Alpha : CallingConv<[
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// The first 6 arguments are passed in registers, whether integer or
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// floating-point
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CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
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[F16, F17, F18, F19, F20, F21]>>,
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CCIfType<[f32, f64], CCAssignToRegWithShadow<[F16, F17, F18, F19, F20, F21],
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[R16, R17, R18, R19, R20, R21]>>,
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// Stack slots are 8 bytes in size and 8-byte aligned.
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CCIfType<[i64, f32, f64], CCAssignToStack<8, 8>>
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]>;
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@ -446,55 +446,9 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
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SDNode *N = Op.getNode();
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SDValue Chain = N->getOperand(0);
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SDValue Addr = N->getOperand(1);
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SDValue InFlag(0,0); // Null incoming flag value.
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SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
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DebugLoc dl = N->getDebugLoc();
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std::vector<SDValue> CallOperands;
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std::vector<MVT> TypeOperands;
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//grab the arguments
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for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
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TypeOperands.push_back(N->getOperand(i).getValueType());
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CallOperands.push_back(N->getOperand(i));
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}
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int count = N->getNumOperands() - 2;
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static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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for (int i = 6; i < count; ++i) {
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unsigned Opc = Alpha::WTF;
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if (TypeOperands[i].isInteger()) {
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Opc = Alpha::STQ;
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} else if (TypeOperands[i] == MVT::f32) {
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Opc = Alpha::STS;
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} else if (TypeOperands[i] == MVT::f64) {
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Opc = Alpha::STT;
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} else
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llvm_unreachable("Unknown operand");
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SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
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CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
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Chain };
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Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0);
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}
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for (int i = 0; i < std::min(6, count); ++i) {
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if (TypeOperands[i].isInteger()) {
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Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i],
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CallOperands[i], InFlag);
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InFlag = Chain.getValue(1);
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} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
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Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i],
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CallOperands[i], InFlag);
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InFlag = Chain.getValue(1);
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} else
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llvm_unreachable("Unknown operand");
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}
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// Finally, once everything is in registers to pass to the call, emit the
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// call itself.
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if (Addr.getOpcode() == AlphaISD::GPRelLo) {
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SDValue GOT = SDValue(getGlobalBaseReg(), 0);
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
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@ -510,31 +464,8 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
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}
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InFlag = Chain.getValue(1);
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std::vector<SDValue> CallResults;
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switch (N->getValueType(0).getSimpleVT()) {
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default: llvm_unreachable("Unexpected ret value!");
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case MVT::Other: break;
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case MVT::i64:
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Chain = CurDAG->getCopyFromReg(Chain, dl,
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Alpha::R0, MVT::i64, InFlag).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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case MVT::f32:
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Chain = CurDAG->getCopyFromReg(Chain, dl,
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Alpha::F0, MVT::f32, InFlag).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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case MVT::f64:
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Chain = CurDAG->getCopyFromReg(Chain, dl,
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Alpha::F0, MVT::f64, InFlag).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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}
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CallResults.push_back(Chain);
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for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
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ReplaceUses(Op.getValue(i), CallResults[i]);
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ReplaceUses(Op.getValue(0), Chain);
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ReplaceUses(Op.getValue(1), InFlag);
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}
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@ -13,12 +13,14 @@
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#include "AlphaISelLowering.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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@ -223,6 +225,174 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
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// //#define GP $29
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// //#define SP $30
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#include "AlphaGenCallingConv.inc"
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SDValue AlphaTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
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SDValue Chain = TheCall->getChain();
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SDValue Callee = TheCall->getCallee();
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned CC = MF.getFunction()->getCallingConv();
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
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CCInfo.AnalyzeCallOperands(TheCall, CC_Alpha);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
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getPointerTy(), true));
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SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
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SmallVector<SDValue, 12> MemOpChains;
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SDValue StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments start after the 5 first operands of ISD::CALL
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SDValue Arg = TheCall->getArg(i);
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at RegsToPass
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// vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(VA.getLocMemOffset()));
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(), 0));
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}
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}
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// Transform all store nodes into one single node because all store nodes are
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// independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emited instructions must be stuck together.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, getPointerTy(), true),
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DAG.getConstant(0, getPointerTy(), true),
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InFlag);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
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Op.getResNo());
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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/// being lowered. Returns a SDNode with the same number of values as the
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/// ISD::CALL.
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SDNode*
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AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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CallSDNode *TheCall,
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unsigned CallingConv,
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SelectionDAG &DAG) {
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = TheCall->getDebugLoc();
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
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DAG.getContext());
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CCInfo.AnalyzeCallResult(TheCall, RetCC_Alpha);
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SmallVector<SDValue, 8> ResultVals;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
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VA.getLocVT(), InFlag).getValue(1);
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SDValue RetValue = Chain.getValue(0);
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InFlag = Chain.getValue(2);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
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ResultVals.push_back(RetValue);
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}
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ResultVals.push_back(Chain);
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// Merge everything together with a MERGE_VALUES node.
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return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
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&ResultVals[0], ResultVals.size()).getNode();
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}
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static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
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int &VarArgsBase,
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int &VarArgsOffset) {
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@ -365,85 +535,6 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
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MVT::Other, Copy, Copy.getValue(1));
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}
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std::pair<SDValue, SDValue>
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AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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bool isInreg, unsigned NumFixedArgs,
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unsigned CallingConv,
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bool isTailCall, SDValue Callee,
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ArgListTy &Args, SelectionDAG &DAG,
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DebugLoc dl) {
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int NumBytes = 0;
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if (Args.size() > 6)
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NumBytes = (Args.size() - 6) * 8;
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
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std::vector<SDValue> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].Ty).getSimpleVT()) {
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default: llvm_unreachable("Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].isSExt)
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Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
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MVT::i64, Args[i].Node);
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else if (Args[i].isZExt)
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Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
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MVT::i64, Args[i].Node);
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else
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Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
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break;
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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break;
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}
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args_to_use.push_back(Args[i].Node);
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}
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std::vector<MVT> RetVals;
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MVT RetTyVT = getValueType(RetTy);
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MVT ActualRetTyVT = RetTyVT;
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if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
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ActualRetTyVT = MVT::i64;
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(ActualRetTyVT);
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RetVals.push_back(MVT::Other);
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std::vector<SDValue> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
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SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
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RetVals, &Ops[0], Ops.size());
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
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DAG.getIntPtrConstant(0, true), SDValue());
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SDValue RetVal = TheCall;
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if (RetTyVT != ActualRetTyVT) {
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ISD::NodeType AssertKind = ISD::DELETED_NODE;
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if (RetSExt)
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AssertKind = ISD::AssertSext;
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else if (RetZExt)
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AssertKind = ISD::AssertZext;
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if (AssertKind != ISD::DELETED_NODE)
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RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
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DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
|
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}
|
||||
|
||||
return std::make_pair(RetVal, Chain);
|
||||
}
|
||||
|
||||
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
|
||||
SDValue &DataPtr, SelectionDAG &DAG) {
|
||||
Chain = N->getOperand(0);
|
||||
@ -482,7 +573,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
||||
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
|
||||
VarArgsBase,
|
||||
VarArgsOffset);
|
||||
|
||||
case ISD::CALL: return LowerCALL(Op, DAG);
|
||||
case ISD::RET: return LowerRET(Op,DAG);
|
||||
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
||||
|
||||
|
||||
@ -82,13 +82,9 @@ namespace llvm {
|
||||
// Friendly names for dumps
|
||||
const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
||||
/// actual call.
|
||||
virtual std::pair<SDValue, SDValue>
|
||||
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
|
||||
bool isVarArg, bool isInreg, unsigned NumFixedArgs, unsigned CC,
|
||||
bool isTailCall, SDValue Callee, ArgListTy &Args,
|
||||
SelectionDAG &DAG, DebugLoc dl);
|
||||
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
|
||||
SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
|
||||
unsigned CallingConv, SelectionDAG &DAG);
|
||||
|
||||
ConstraintType getConstraintType(const std::string &Constraint) const;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user