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Move base value of instruction to lookup table to prepare for case reduction.
llvm-svn: 29122
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0d4c198ecd
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@ -77,21 +77,30 @@ void CodeEmitterGen::run(std::ostream &o) {
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EmitSourceFileHeader("Machine Code Emitter", o);
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std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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// Emit function declaration
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o << "unsigned " << Target.getName() << "CodeEmitter::"
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<< "getBinaryCodeForInstr(MachineInstr &MI) {\n"
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<< " unsigned Value = 0;\n"
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<< " switch (MI.getOpcode()) {\n";
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<< "getBinaryCodeForInstr(MachineInstr &MI) {\n";
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// Emit a case statement for each opcode
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
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// Emit instruction base values
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o << " static const unsigned InstBits[] = {\n";
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for (std::vector<const CodeGenInstruction*>::iterator
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IN = NumberedInstructions.begin(),
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EN = NumberedInstructions.end();
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IN != EN; ++IN) {
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const CodeGenInstruction *CGI = *IN;
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Record *R = CGI->TheDef;
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if (IN != NumberedInstructions.begin()) o << ",\n";
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if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
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o << " 0U";
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continue;
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}
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o << " case " << Namespace << R->getName() << ": {\n";
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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// For little-endian instruction bit encodings, reverse the bit order
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@ -119,20 +128,31 @@ void CodeEmitterGen::run(std::ostream &o) {
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unsigned Value = 0;
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const std::vector<RecordVal> &Vals = R->getValues();
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DEBUG(o << " // prefilling: ");
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// Start by filling in fixed values...
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
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Value |= B->getValue() << (e-i-1);
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DEBUG(o << B->getValue());
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} else {
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DEBUG(o << "0");
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}
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}
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DEBUG(o << "\n");
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o << " " << Value << "U";
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}
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o << "\n };\n";
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DEBUG(o << " // " << *R->getValue("Inst") << "\n");
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o << " Value = " << Value << "U;\n\n";
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// Emit initial function code
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o << " const unsigned opcode = MI.getOpcode();\n"
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<< " unsigned Value = InstBits[opcode];\n"
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<< " switch (opcode) {\n";
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// Emit a case statement for each opcode
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
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o << " case " << Namespace << R->getName() << ": {\n";
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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const std::vector<RecordVal> &Vals = R->getValues();
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// Loop over all of the fields in the instruction, determining which are the
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// operands to the instruction.
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