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https://github.com/RPCS3/llvm-mirror.git
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Correct word hyphenations
This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471
This commit is contained in:
Alp Toker
parent
b4226966a9
commit
e845f8af67
@ -844,7 +844,7 @@ Here are more examples:
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.. code-block:: c++
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assert(Ty->isPointerType() && "Can't allocate a non pointer type!");
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assert(Ty->isPointerType() && "Can't allocate a non-pointer type!");
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assert((Opcode == Shl || Opcode == Shr) && "ShiftInst Opcode invalid!");
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@ -1276,7 +1276,7 @@ The ``cl::getRegisteredOptions`` function
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``cl::getRegisteredOptions`` function is designed to give a programmer
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access to declared non positional command line options so that how they appear
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access to declared non-positional command line options so that how they appear
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in ``-help`` can be modified prior to calling `cl::ParseCommandLineOptions`_.
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Note this method should not be called during any static initialisation because
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it cannot be guaranteed that all options will have been initialised. Hence it
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@ -612,7 +612,7 @@ Syntax::
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The linkage must be one of ``private``, ``linker_private``,
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``linker_private_weak``, ``internal``, ``linkonce``, ``weak``,
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``linkonce_odr``, ``weak_odr``, ``external``. Note that some system linkers
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might not correctly handle dropping a weak symbol that is aliased by a non weak
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might not correctly handle dropping a weak symbol that is aliased by a non-weak
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alias.
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.. _namedmetadatastructure:
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@ -2306,7 +2306,7 @@ stringWithCString:]``") and the basename is the selector only
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Mach-O Changes
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""""""""""""""
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The sections names for the apple hash tables are for non mach-o files. For
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The sections names for the apple hash tables are for non-mach-o files. For
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mach-o files, the sections should be contained in the ``__DWARF`` segment with
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names as follows:
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@ -382,7 +382,7 @@ class SparseBitVector {
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AtEnd = true;
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return;
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}
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// Set up for next non zero word in bitmap.
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// Set up for next non-zero word in bitmap.
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BitNumber = Iter->index() * ElementSize;
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NextSetBitNumber = Iter->find_first();
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BitNumber += NextSetBitNumber;
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@ -34,7 +34,7 @@ namespace llvm {
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// IntervalPartition - This class builds and holds an "interval partition" for
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// a function. This partition divides the control flow graph into a set of
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// maximal intervals, as defined with the properties above. Intuitively, an
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// interval is a (possibly nonexistent) loop with a "tail" of non looping
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// interval is a (possibly nonexistent) loop with a "tail" of non-looping
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// nodes following it.
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//
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class IntervalPartition : public FunctionPass {
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@ -312,11 +312,11 @@ public:
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/// The toplevel region represents the whole function.
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bool isTopLevelRegion() const { return exit == NULL; }
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/// @brief Return a new (non canonical) region, that is obtained by joining
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/// @brief Return a new (non-canonical) region, that is obtained by joining
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/// this region with its predecessors.
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///
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/// @return A region also starting at getEntry(), but reaching to the next
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/// basic block that forms with getEntry() a (non canonical) region.
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/// basic block that forms with getEntry() a (non-canonical) region.
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/// NULL if such a basic block does not exist.
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Region *getExpandedRegion() const;
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@ -43,7 +43,7 @@ namespace llvm {
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};
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/// Record a physical register access.
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/// For non data-dependent uses, OpIdx == -1.
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/// For non-data-dependent uses, OpIdx == -1.
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struct PhysRegSUOper {
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SUnit *SU;
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int OpIdx;
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@ -82,7 +82,7 @@ namespace llvm {
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/// LinkerRequiresNonEmptyDwarfLines - True if the linker has a bug and
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/// requires that the debug_line section be of a minimum size. In practice
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/// such a linker requires a non empty line sequence if a file is present.
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/// such a linker requires a non-empty line sequence if a file is present.
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bool LinkerRequiresNonEmptyDwarfLines; // Default to false.
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/// MaxInstLength - This is the maximum possible length of an instruction,
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@ -141,7 +141,7 @@ namespace llvm {
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}
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// AliasedSymbol() - If this is an alias (a = b), return the symbol
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// we ultimately point to. For a non alias, this just returns the symbol
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// we ultimately point to. For a non-alias, this just returns the symbol
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// itself.
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const MCSymbol &AliasedSymbol() const;
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@ -34,7 +34,7 @@ class PredIterator : public std::iterator<std::forward_iterator_tag,
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USE_iterator It;
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inline void advancePastNonTerminators() {
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// Loop to ignore non terminator uses (for example BlockAddresses).
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// Loop to ignore non-terminator uses (for example BlockAddresses).
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while (!It.atEnd() && !isa<TerminatorInst>(*It))
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++It;
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}
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@ -880,13 +880,13 @@ protected:
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}
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/// Indicate whether this target prefers to use _setjmp to implement
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/// llvm.setjmp or the non _ version. Defaults to false.
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/// llvm.setjmp or the version without _. Defaults to false.
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void setUseUnderscoreSetJmp(bool Val) {
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UseUnderscoreSetJmp = Val;
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}
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/// Indicate whether this target prefers to use _longjmp to implement
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/// llvm.longjmp or the non _ version. Defaults to false.
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/// llvm.longjmp or the version without _. Defaults to false.
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void setUseUnderscoreLongJmp(bool Val) {
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UseUnderscoreLongJmp = Val;
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}
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@ -72,7 +72,7 @@ static bool VerifySubExpr(Value *Expr,
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// If it isn't in the InstInputs list it is a subexpr incorporated into the
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// address. Sanity check that it is phi translatable.
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if (!CanPHITrans(I)) {
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errs() << "Non phi translatable instruction found in PHITransAddr:\n";
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errs() << "Instruction in PHITransAddr is not phi-translatable:\n";
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errs() << *I << '\n';
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llvm_unreachable("Either something is missing from InstInputs or "
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"CanPHITrans is wrong.");
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@ -1528,7 +1528,7 @@ Value *SCEVExpander::expand(const SCEV *S) {
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//
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// This is independent of PostIncLoops. The mapped value simply materializes
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// the expression at this insertion point. If the mapped value happened to be
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// a postinc expansion, it could be reused by a non postinc user, but only if
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// a postinc expansion, it could be reused by a non-postinc user, but only if
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// its insertion point was already at the head of the loop.
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InsertedExpressions[std::make_pair(S, InsertPt)] = V;
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return V;
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@ -690,7 +690,7 @@ void ScheduleDAGInstrs::initSUnits() {
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}
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}
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/// If RegPressure is non null, compute register pressure as a side effect. The
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/// If RegPressure is non-null, compute register pressure as a side effect. The
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/// DAG builder is an efficient place to do it because it already visits
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/// operands.
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void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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@ -8120,7 +8120,7 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) {
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// The width of the type must be a power of 2 and greater than 8-bits.
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// Otherwise the load cannot be represented in LLVM IR.
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// Moreover, if we shifted with a non 8-bits multiple, the slice
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// Moreover, if we shifted with a non-8-bits multiple, the slice
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// will be accross several bytes. We do not support that.
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unsigned Width = User->getValueSizeInBits(0);
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if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
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@ -8762,7 +8762,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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} else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
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NonZero |= !C->getConstantFPValue()->isNullValue();
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} else {
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// Non constant.
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// Non-constant.
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break;
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}
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@ -670,13 +670,13 @@ private:
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LoadSDNode *LD, ISD::LoadExtType ExtType);
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/// Helper genWidenVectorStores - Helper function to generate a set of
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/// stores to store a widen vector into non widen memory
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/// stores to store a widen vector into non-widen memory
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/// StChain: list of chains for the stores we have generated
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/// ST: store of a widen value
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void GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);
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/// Helper genWidenVectorTruncStores - Helper function to generate a set of
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/// stores to store a truncate widen vector into non widen memory
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/// stores to store a truncate widen vector into non-widen memory
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/// StChain: list of chains for the stores we have generated
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/// ST: store of a widen value
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void GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
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@ -2251,7 +2251,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
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SDValue InOp1 = N->getOperand(0);
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EVT InVT = InOp1.getValueType();
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assert(InVT.isVector() && "can not widen non vector type");
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assert(InVT.isVector() && "can not widen non-vector type");
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EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
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InVT.getVectorElementType(), WidenNumElts);
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InOp1 = GetWidenedVector(InOp1);
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@ -452,7 +452,7 @@ void StackColoring::calculateLiveIntervals(unsigned NumSlots) {
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// We have a single consecutive region.
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Intervals[i]->addSegment(LiveInterval::Segment(S, F, ValNum));
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} else {
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// We have two non consecutive regions. This happens when
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// We have two non-consecutive regions. This happens when
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// LIFETIME_START appears after the LIFETIME_END marker.
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SlotIndex NewStart = Indexes->getMBBStartIdx(MBB);
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SlotIndex NewFin = Indexes->getMBBEndIdx(MBB);
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@ -2206,7 +2206,7 @@ unsigned CastInst::isEliminableCastPair(
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case 3:
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// No-op cast in second op implies firstOp as long as the DestTy
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// is integer and we are not converting between a vector and a
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// non vector type.
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// non-vector type.
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if (!SrcTy->isVectorTy() && DstTy->isIntegerTy())
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return firstOp;
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return 0;
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@ -2823,7 +2823,7 @@ CastInst::castIsValid(Instruction::CastOps op, Value *S, Type *DstTy) {
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if (SrcTy->isPtrOrPtrVectorTy() != DstTy->isPtrOrPtrVectorTy())
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return false;
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// For non pointer cases, the cast is okay if the source and destination bit
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// For non-pointer cases, the cast is okay if the source and destination bit
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// widths are identical.
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if (!SrcTy->isPtrOrPtrVectorTy())
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return SrcTy->getPrimitiveSizeInBits() == DstTy->getPrimitiveSizeInBits();
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@ -475,7 +475,7 @@ public:
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}
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// createTheTimeInfo - This method either initializes the TheTimeInfo pointer
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// to a non null value (if the -time-passes option is enabled) or it leaves it
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// to a non-null value (if the -time-passes option is enabled) or it leaves it
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// null. It may be called multiple times.
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static void createTheTimeInfo();
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@ -1755,7 +1755,7 @@ EnableTiming("time-passes", cl::location(TimePassesIsEnabled),
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cl::desc("Time each pass, printing elapsed time for each on exit"));
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// createTheTimeInfo - This method either initializes the TheTimeInfo pointer to
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// a non null value (if the -time-passes option is enabled) or it leaves it
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// a non-null value (if the -time-passes option is enabled) or it leaves it
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// null. It may be called multiple times.
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void TimingInfo::createTheTimeInfo() {
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if (!TimePassesIsEnabled || TheTimeInfo) return;
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@ -138,7 +138,7 @@ MCSymbol *MCContext::CreateSymbol(StringRef Name) {
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StringMapEntry<bool> *NameEntry = &UsedNames.GetOrCreateValue(Name);
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if (NameEntry->getValue()) {
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assert(isTemporary && "Cannot rename non temporary symbols");
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assert(isTemporary && "Cannot rename non-temporary symbols");
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SmallString<128> NewName = Name;
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do {
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NewName.resize(Name.size());
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@ -68,7 +68,7 @@ ENTRY(0 /*FIXME*/, S_ATTR_EXT_RELOC)
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ENTRY(0 /*FIXME*/, S_ATTR_LOC_RELOC)
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#undef ENTRY
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{ 0, "none", 0 }, // used if section has no attributes but has a stub size
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#define AttrFlagEnd 0xffffffff // non legal value, multiple attribute bits set
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#define AttrFlagEnd 0xffffffff // non-legal value, multiple attribute bits set
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{ AttrFlagEnd, 0, 0 }
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};
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@ -446,7 +446,7 @@ void MachObjectWriter::BindIndirectSymbols(MCAssembler &Asm) {
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}
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}
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// Bind non lazy symbol pointers first.
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// Bind non-lazy symbol pointers first.
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unsigned IndirectIndex = 0;
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for (MCAssembler::indirect_symbol_iterator it = Asm.indirect_symbol_begin(),
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ie = Asm.indirect_symbol_end(); it != ie; ++it, ++IndirectIndex) {
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@ -917,7 +917,7 @@ void MachObjectWriter::WriteObject(MCAssembler &Asm,
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for (MCAssembler::const_indirect_symbol_iterator
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it = Asm.indirect_symbol_begin(),
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ie = Asm.indirect_symbol_end(); it != ie; ++it) {
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// Indirect symbols in the non lazy symbol pointer section have some
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// Indirect symbols in the non-lazy symbol pointer section have some
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// special handling.
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const MCSectionMachO &Section =
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static_cast<const MCSectionMachO&>(it->SectionData->getSection());
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@ -351,7 +351,7 @@ object_t *WinCOFFObjectWriter::createCOFFEntity(StringRef Name,
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/// and creates the associated COFF section staging object.
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void WinCOFFObjectWriter::DefineSection(MCSectionData const &SectionData) {
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assert(SectionData.getSection().getVariant() == MCSection::SV_COFF
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&& "Got non COFF section in the COFF backend!");
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&& "Got non-COFF section in the COFF backend!");
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// FIXME: Not sure how to verify this (at least in a debug build).
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MCSectionCOFF const &Sec =
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static_cast<MCSectionCOFF const &>(SectionData.getSection());
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@ -190,7 +190,7 @@ bool WinCOFFStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
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assert(Symbol && "Symbol must be non-null!");
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assert((Symbol->isInSection()
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? Symbol->getSection().getVariant() == MCSection::SV_COFF
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: true) && "Got non COFF section in the COFF backend!");
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: true) && "Got non-COFF section in the COFF backend!");
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switch (Attribute) {
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case MCSA_WeakReference:
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case MCSA_Weak: {
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@ -218,7 +218,7 @@ void WinCOFFStreamer::EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) {
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void WinCOFFStreamer::BeginCOFFSymbolDef(MCSymbol const *Symbol) {
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assert((Symbol->isInSection()
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? Symbol->getSection().getVariant() == MCSection::SV_COFF
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: true) && "Got non COFF section in the COFF backend!");
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: true) && "Got non-COFF section in the COFF backend!");
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assert(CurSymbol == NULL && "EndCOFFSymbolDef must be called between calls "
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"to BeginCOFFSymbolDef!");
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CurSymbol = Symbol;
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@ -268,7 +268,7 @@ void WinCOFFStreamer::EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment) {
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assert((Symbol->isInSection()
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? Symbol->getSection().getVariant() == MCSection::SV_COFF
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: true) && "Got non COFF section in the COFF backend!");
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: true) && "Got non-COFF section in the COFF backend!");
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AddCommonSymbol(Symbol, Size, ByteAlignment, true);
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}
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@ -276,7 +276,7 @@ void WinCOFFStreamer::EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment) {
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assert((Symbol->isInSection()
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? Symbol->getSection().getVariant() == MCSection::SV_COFF
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: true) && "Got non COFF section in the COFF backend!");
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: true) && "Got non-COFF section in the COFF backend!");
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AddCommonSymbol(Symbol, Size, ByteAlignment, false);
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}
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@ -3816,7 +3816,7 @@ APFloat::opStatus APFloat::next(bool nextDown) {
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// Decrement the significand.
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//
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// We always do this since:
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// 1. If we are dealing with a non binade decrement, by definition we
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// 1. If we are dealing with a non-binade decrement, by definition we
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// just decrement the significand.
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// 2. If we are dealing with a normal -> normal binade decrement, since
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// we have an explicit integral bit the fact that all bits but the
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@ -645,7 +645,7 @@ uint64_t mapped_file_region::size() const {
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char *mapped_file_region::data() const {
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assert(Mapping && "Mapping failed but used anyway!");
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assert(Mode != readonly && "Cannot get non const data for readonly mapping!");
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assert(Mode != readonly && "Cannot get non-const data for readonly mapping!");
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return reinterpret_cast<char*>(Mapping);
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}
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@ -859,7 +859,7 @@ uint64_t mapped_file_region::size() const {
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}
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char *mapped_file_region::data() const {
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assert(Mode != readonly && "Cannot get non const data for readonly mapping!");
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assert(Mode != readonly && "Cannot get non-const data for readonly mapping!");
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assert(Mapping && "Mapping failed but used anyway!");
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return reinterpret_cast<char*>(Mapping);
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}
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@ -165,7 +165,7 @@ unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
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if (!MI) return ARM::ssub_0;
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MachineOperand *MO = MI->findRegisterDefOperand(SReg);
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assert(MO->isReg() && "Non register operand found!");
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assert(MO->isReg() && "Non-register operand found!");
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if (!MO) return ARM::ssub_0;
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if (MI->isCopy() && usesRegClass(MI->getOperand(1),
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@ -2802,7 +2802,7 @@ ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
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bool ForceMutable) const {
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// Currently, two use-cases possible:
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// Case #1. Non var-args function, and we meet first byval parameter.
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// Case #1. Non-var-args function, and we meet first byval parameter.
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// Setup first unallocated register as first byval register;
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// eat all remained registers
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// (these two actions are performed by HandleByVal method).
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@ -2217,7 +2217,7 @@ def A9WriteLMfp : SchedWriteVariant<[
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SchedVar<A9PostRA, [A9WriteLMfpPostRA]>]>;
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//===----------------------------------------------------------------------===//
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// Resources for other (non LDM/VLDM) Variants.
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// Resources for other (non-LDM/VLDM) Variants.
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// These mov immediate writers are unconditionally expanded with
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// additive latency.
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||||
|
||||
@ -145,7 +145,7 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
|
||||
SDValue Src, SDValue Size,
|
||||
unsigned Align, bool isVolatile,
|
||||
MachinePointerInfo DstPtrInfo) const {
|
||||
// Use default for non AAPCS (or Darwin) subtargets
|
||||
// Use default for non-AAPCS (or Darwin) subtargets
|
||||
if (!Subtarget->isAAPCS_ABI() || Subtarget->isTargetDarwin())
|
||||
return SDValue();
|
||||
|
||||
|
||||
@ -1580,7 +1580,7 @@ public:
|
||||
void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
|
||||
assert(N == 3 && "Invalid number of operands!");
|
||||
assert(isRegShiftedReg() &&
|
||||
"addRegShiftedRegOperands() on non RegShiftedReg!");
|
||||
"addRegShiftedRegOperands() on non-RegShiftedReg!");
|
||||
Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
|
||||
Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
|
||||
Inst.addOperand(MCOperand::CreateImm(
|
||||
@ -1590,7 +1590,7 @@ public:
|
||||
void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
|
||||
assert(N == 2 && "Invalid number of operands!");
|
||||
assert(isRegShiftedImm() &&
|
||||
"addRegShiftedImmOperands() on non RegShiftedImm!");
|
||||
"addRegShiftedImmOperands() on non-RegShiftedImm!");
|
||||
Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
|
||||
// Shift of #32 is encoded as 0 where permitted
|
||||
unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
|
||||
|
||||
@ -1639,7 +1639,7 @@ bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Return true if the non GP-relative global address can be folded.
|
||||
// Return true if the non-GP-relative global address can be folded.
|
||||
//===--------------------------------------------------------------------===//
|
||||
inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
|
||||
return foldGlobalAddressImpl(N, R, false);
|
||||
|
||||
@ -1539,7 +1539,7 @@ int HexagonInstrInfo::GetDotOldOp(const int opc) const {
|
||||
assert(0 && "Couldn't change predicate new instruction to its old form.");
|
||||
}
|
||||
|
||||
if (isNewValueStore(NewOp)) { // Convert into non new-value format
|
||||
if (isNewValueStore(NewOp)) { // Convert into non-new-value format
|
||||
NewOp = Hexagon::getNonNVStore(NewOp);
|
||||
if (NewOp < 0)
|
||||
assert(0 && "Couldn't change new-value store to its old form.");
|
||||
|
||||
@ -1016,7 +1016,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
|
||||
bits<5> src1;
|
||||
bits<5> src2;
|
||||
bits<3> Ns; // New-Value Operand
|
||||
bits<5> RegOp; // Non New-Value Operand
|
||||
bits<5> RegOp; // Non-New-Value Operand
|
||||
bits<11> offset;
|
||||
|
||||
let isBrTaken = !if(isTaken, "true", "false");
|
||||
|
||||
@ -681,7 +681,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
|
||||
}
|
||||
}
|
||||
|
||||
// Make sure that for non POST_INC stores:
|
||||
// Make sure that for non-POST_INC stores:
|
||||
// 1. The only use of reg is DepReg and no other registers.
|
||||
// This handles V4 base+index registers.
|
||||
// The following store can not be dot new.
|
||||
|
||||
@ -41,7 +41,7 @@ static bool CC_Hexagon32_VarArgs(unsigned ValNo, EVT ValVT,
|
||||
}
|
||||
|
||||
|
||||
// Only assign registers for named (non varargs) arguments
|
||||
// Only assign registers for named (non-varargs) arguments
|
||||
if ( !ForceMem && ((NonVarArgsParams == -1) || (CurrentParam <=
|
||||
NonVarArgsParams))) {
|
||||
|
||||
|
||||
@ -298,7 +298,7 @@ class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
|
||||
|
||||
//
|
||||
// This are pseudo formats for multiply
|
||||
// This first one can be changed to non pseudo now.
|
||||
// This first one can be changed to non-pseudo now.
|
||||
//
|
||||
// MULT
|
||||
//
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
//
|
||||
// The constants can be not just numbers but addresses of functions and labels.
|
||||
// This can be particularly helpful in static relocation mode for embedded
|
||||
// non linux targets.
|
||||
// non-linux targets.
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
@ -1580,7 +1580,7 @@ void NVPTXAsmPrinter::emitFunctionParamList(const Function *F, raw_ostream &O) {
|
||||
continue;
|
||||
}
|
||||
// Non-kernel function, just print .param .b<size> for ABI
|
||||
// and .reg .b<size> for non ABY
|
||||
// and .reg .b<size> for non-ABI
|
||||
unsigned sz = 0;
|
||||
if (isa<IntegerType>(Ty)) {
|
||||
sz = cast<IntegerType>(Ty)->getBitWidth();
|
||||
|
||||
@ -2968,7 +2968,7 @@ PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
|
||||
if (Flags.isByVal()) return false;
|
||||
}
|
||||
|
||||
// Non PIC/GOT tail calls are supported.
|
||||
// Non-PIC/GOT tail calls are supported.
|
||||
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
|
||||
return true;
|
||||
|
||||
|
||||
@ -1239,7 +1239,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
|
||||
}
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
|
||||
} else {
|
||||
// non constant ptr cant be folded, keeps it as a v4f32 load
|
||||
// non-constant ptr can't be folded, keeps it as a v4f32 load
|
||||
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
|
||||
DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
|
||||
DAG.getConstant(LoadNode->getAddressSpace() -
|
||||
|
||||
@ -205,7 +205,7 @@ void SIAnnotateControlFlow::insertElse(BranchInst *Term) {
|
||||
void SIAnnotateControlFlow::handleLoopCondition(Value *Cond) {
|
||||
if (PHINode *Phi = dyn_cast<PHINode>(Cond)) {
|
||||
|
||||
// Handle all non constant incoming values first
|
||||
// Handle all non-constant incoming values first
|
||||
for (unsigned i = 0, e = Phi->getNumIncomingValues(); i != e; ++i) {
|
||||
Value *Incoming = Phi->getIncomingValue(i);
|
||||
if (isa<ConstantInt>(Incoming))
|
||||
|
||||
@ -314,7 +314,7 @@ bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
|
||||
{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
|
||||
};
|
||||
|
||||
// This CPU doesnt support long nops. If needed add more.
|
||||
// This CPU doesn't support long nops. If needed add more.
|
||||
// FIXME: Can we get this from the subtarget somehow?
|
||||
// FIXME: We could generated something better than plain 0x90.
|
||||
if (!HasNopl) {
|
||||
|
||||
@ -344,7 +344,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
|
||||
// addl %gs:0, %eax
|
||||
// if the block also has an access to a second TLS address this will save
|
||||
// a load.
|
||||
// FIXME: This is probably also true for non TLS addresses.
|
||||
// FIXME: This is probably also true for non-TLS addresses.
|
||||
if (Op1.getOpcode() == X86ISD::Wrapper) {
|
||||
SDValue Val = Op1.getOperand(0);
|
||||
if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
|
||||
|
||||
@ -555,7 +555,7 @@ unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
|
||||
|
||||
unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
||||
unsigned AddressSpace) const {
|
||||
// Handle non power of two vectors such as <3 x float>
|
||||
// Handle non-power-of-two vectors such as <3 x float>
|
||||
if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
|
||||
unsigned NumElem = VTy->getVectorNumElements();
|
||||
|
||||
@ -570,7 +570,7 @@ unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
||||
// Cost = 128 bit store + unpack + 64 bit store.
|
||||
return 3;
|
||||
|
||||
// Assume that all other non power-of-two numbers are scalarized.
|
||||
// Assume that all other non-power-of-two numbers are scalarized.
|
||||
if (!isPowerOf2_32(NumElem)) {
|
||||
unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
|
||||
VTy->getScalarType(),
|
||||
|
||||
@ -1737,7 +1737,7 @@ bool GlobalOpt::ProcessInternalGlobal(GlobalVariable *GV,
|
||||
// and this function is main (which we know is not recursive), we replace
|
||||
// the global with a local alloca in this function.
|
||||
//
|
||||
// NOTE: It doesn't make sense to promote non single-value types since we
|
||||
// NOTE: It doesn't make sense to promote non-single-value types since we
|
||||
// are just replacing static memory to stack memory.
|
||||
//
|
||||
// If the global is in different address space, don't bring it to stack.
|
||||
@ -2571,7 +2571,7 @@ bool Evaluator::EvaluateBlock(BasicBlock::iterator CurInst,
|
||||
// We don't insert an entry into Values, as it doesn't have a
|
||||
// meaningful return value.
|
||||
if (!II->use_empty()) {
|
||||
DEBUG(dbgs() << "Found unused invariant_start. Cant evaluate.\n");
|
||||
DEBUG(dbgs() << "Found unused invariant_start. Can't evaluate.\n");
|
||||
return false;
|
||||
}
|
||||
ConstantInt *Size = cast<ConstantInt>(II->getArgOperand(0));
|
||||
|
||||
@ -210,7 +210,7 @@ bool IPCP::PropagateConstantReturn(Function &F) {
|
||||
// Different or no known return value? Don't propagate this return
|
||||
// value.
|
||||
RetVals[i] = 0;
|
||||
// All values non constant? Stop looking.
|
||||
// All values non-constant? Stop looking.
|
||||
if (++NumNonConstant == RetVals.size())
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -147,7 +147,7 @@ static void RemoveDeadConstant(Constant *C) {
|
||||
if (OnlyUsedBy(C->getOperand(i), C))
|
||||
Operands.insert(cast<Constant>(C->getOperand(i)));
|
||||
if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) {
|
||||
if (!GV->hasLocalLinkage()) return; // Don't delete non static globals.
|
||||
if (!GV->hasLocalLinkage()) return; // Don't delete non-static globals.
|
||||
GV->eraseFromParent();
|
||||
}
|
||||
else if (!isa<Function>(C))
|
||||
|
||||
@ -1005,7 +1005,7 @@ static void GenerateARCAnnotation(unsigned InstMDId,
|
||||
// llvm-arc-annotation-processor tool to cross reference where the source
|
||||
// pointer is in the LLVM IR since the LLVM IR parser does not submit such
|
||||
// information via debug info for backends to use (since why would anyone
|
||||
// need such a thing from LLVM IR besides in non standard cases
|
||||
// need such a thing from LLVM IR besides in non-standard cases
|
||||
// [i.e. this]).
|
||||
MDString *SourcePtrMDNode =
|
||||
AppendMDNodeToSourcePtr(PtrMDId, Ptr);
|
||||
|
||||
@ -1789,7 +1789,7 @@ static void patchReplacementInstruction(Instruction *I, Value *Repl) {
|
||||
ReplInst->setMetadata(Kind, MDNode::getMostGenericRange(IMD, ReplMD));
|
||||
break;
|
||||
case LLVMContext::MD_prof:
|
||||
llvm_unreachable("MD_prof in a non terminator instruction");
|
||||
llvm_unreachable("MD_prof in a non-terminator instruction");
|
||||
break;
|
||||
case LLVMContext::MD_fpmath:
|
||||
ReplInst->setMetadata(Kind, MDNode::getMostGenericFPMath(IMD, ReplMD));
|
||||
|
||||
@ -301,7 +301,7 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) {
|
||||
CodeMetrics Metrics;
|
||||
Metrics.analyzeBasicBlock(OrigHeader, *TTI);
|
||||
if (Metrics.notDuplicatable) {
|
||||
DEBUG(dbgs() << "LoopRotation: NOT rotating - contains non duplicatable"
|
||||
DEBUG(dbgs() << "LoopRotation: NOT rotating - contains non-duplicatable"
|
||||
<< " instructions: "; L->dump());
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -213,7 +213,7 @@ bool LoopUnroll::runOnLoop(Loop *L, LPPassManager &LPM) {
|
||||
notDuplicatable, TTI);
|
||||
DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n");
|
||||
if (notDuplicatable) {
|
||||
DEBUG(dbgs() << " Not unrolling loop which contains non duplicatable"
|
||||
DEBUG(dbgs() << " Not unrolling loop which contains non-duplicatable"
|
||||
<< " instructions.\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -1731,7 +1731,7 @@ void SROA::isSafeGEP(GetElementPtrInst *GEPI,
|
||||
// Compute the offset due to this GEP and check if the alloca has a
|
||||
// component element at that offset.
|
||||
SmallVector<Value*, 8> Indices(GEPI->op_begin() + 1, GEPI->op_end());
|
||||
// If this GEP is non constant then the last operand must have been a
|
||||
// If this GEP is non-constant then the last operand must have been a
|
||||
// dynamic index into a vector. Pop this now as it has no impact on the
|
||||
// constant part of the offset.
|
||||
if (NonConstant)
|
||||
|
||||
@ -679,8 +679,8 @@ void PromoteMem2Reg::run() {
|
||||
|
||||
// Iterating over NewPhiNodes is deterministic, so it is safe to try to
|
||||
// simplify and RAUW them as we go. If it was not, we could add uses to
|
||||
// the values we replace with in a non deterministic order, thus creating
|
||||
// non deterministic def->use chains.
|
||||
// the values we replace with in a non-deterministic order, thus creating
|
||||
// non-deterministic def->use chains.
|
||||
for (DenseMap<std::pair<unsigned, unsigned>, PHINode *>::iterator
|
||||
I = NewPhiNodes.begin(),
|
||||
E = NewPhiNodes.end();
|
||||
|
||||
@ -564,7 +564,7 @@ public:
|
||||
/// pointer itself is an induction variable.
|
||||
/// This check allows us to vectorize A[idx] into a wide load/store.
|
||||
/// Returns:
|
||||
/// 0 - Stride is unknown or non consecutive.
|
||||
/// 0 - Stride is unknown or non-consecutive.
|
||||
/// 1 - Address is consecutive.
|
||||
/// -1 - Address is consecutive, and decreasing.
|
||||
int isConsecutivePtr(Value *Ptr);
|
||||
@ -1093,7 +1093,7 @@ static unsigned getGEPInductionOperand(DataLayout *DL,
|
||||
}
|
||||
|
||||
int LoopVectorizationLegality::isConsecutivePtr(Value *Ptr) {
|
||||
assert(Ptr->getType()->isPointerTy() && "Unexpected non ptr");
|
||||
assert(Ptr->getType()->isPointerTy() && "Unexpected non-ptr");
|
||||
// Make sure that the pointer does not point to structs.
|
||||
if (Ptr->getType()->getPointerElementType()->isAggregateType())
|
||||
return 0;
|
||||
@ -1216,7 +1216,7 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr,
|
||||
if (ScalarAllocatedSize != VectorElementSize)
|
||||
return scalarizeInstruction(Instr);
|
||||
|
||||
// If the pointer is loop invariant or if it is non consecutive,
|
||||
// If the pointer is loop invariant or if it is non-consecutive,
|
||||
// scalarize the load.
|
||||
int ConsecutiveStride = Legal->isConsecutivePtr(Ptr);
|
||||
bool Reverse = ConsecutiveStride < 0;
|
||||
@ -2430,7 +2430,7 @@ void InnerLoopVectorizer::widenPHIInstruction(Instruction *PN,
|
||||
setDebugLocFromInst(Builder, P);
|
||||
// Check for PHI nodes that are lowered to vector selects.
|
||||
if (P->getParent() != OrigLoop->getHeader()) {
|
||||
// We know that all PHIs in non header blocks are converted into
|
||||
// We know that all PHIs in non-header blocks are converted into
|
||||
// selects, so we don't have to worry about the insertion order and we
|
||||
// can just use the builder.
|
||||
// At this point we generate the predication tree. There may be
|
||||
@ -2846,7 +2846,7 @@ bool LoopVectorizationLegality::canVectorize() {
|
||||
DEBUG(dbgs() << "LV: Found a loop: " <<
|
||||
TheLoop->getHeader()->getName() << '\n');
|
||||
|
||||
// Check if we can if-convert non single-bb loops.
|
||||
// Check if we can if-convert non-single-bb loops.
|
||||
unsigned NumBlocks = TheLoop->getNumBlocks();
|
||||
if (NumBlocks != 1 && !canVectorizeWithIfConvert()) {
|
||||
DEBUG(dbgs() << "LV: Can't if-convert the loop.\n");
|
||||
@ -3499,7 +3499,7 @@ private:
|
||||
// We can access this many bytes in parallel safely.
|
||||
unsigned MaxSafeDepDistBytes;
|
||||
|
||||
/// \brief If we see a non constant dependence distance we can still try to
|
||||
/// \brief If we see a non-constant dependence distance we can still try to
|
||||
/// vectorize this loop with runtime checks.
|
||||
bool ShouldRetryWithRuntimeCheck;
|
||||
|
||||
@ -3535,7 +3535,7 @@ static bool isInBoundsGep(Value *Ptr) {
|
||||
static int isStridedPtr(ScalarEvolution *SE, DataLayout *DL, Value *Ptr,
|
||||
const Loop *Lp) {
|
||||
const Type *Ty = Ptr->getType();
|
||||
assert(Ty->isPointerTy() && "Unexpected non ptr");
|
||||
assert(Ty->isPointerTy() && "Unexpected non-ptr");
|
||||
|
||||
// Make sure that the pointer does not point to aggregate types.
|
||||
const PointerType *PtrTy = cast<PointerType>(Ty);
|
||||
@ -3699,7 +3699,7 @@ bool MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
|
||||
|
||||
const SCEVConstant *C = dyn_cast<SCEVConstant>(Dist);
|
||||
if (!C) {
|
||||
DEBUG(dbgs() << "LV: Dependence because of non constant distance\n");
|
||||
DEBUG(dbgs() << "LV: Dependence because of non-constant distance\n");
|
||||
ShouldRetryWithRuntimeCheck = true;
|
||||
return true;
|
||||
}
|
||||
@ -4140,7 +4140,7 @@ bool LoopVectorizationLegality::AddReductionVar(PHINode *Phi,
|
||||
// Check whether we found a reduction operator.
|
||||
FoundReduxOp |= !IsAPhi;
|
||||
|
||||
// Process users of current instruction. Push non PHI nodes after PHI nodes
|
||||
// Process users of current instruction. Push non-PHI nodes after PHI nodes
|
||||
// onto the stack. This way we are going to have seen all inputs to PHI
|
||||
// nodes once we get to them.
|
||||
SmallVector<Instruction *, 8> NonPHIs;
|
||||
|
||||
@ -932,7 +932,7 @@ void BoUpSLP::buildTree_rec(ArrayRef<Value *> VL, unsigned Depth) {
|
||||
for (unsigned i = 0, e = VL.size() - 1; i < e; ++i)
|
||||
if (!isConsecutiveAccess(VL[i], VL[i + 1])) {
|
||||
newTreeEntry(VL, false);
|
||||
DEBUG(dbgs() << "SLP: Non consecutive store.\n");
|
||||
DEBUG(dbgs() << "SLP: Non-consecutive store.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
|
||||
|
||||
; Check vector comparisons using altivec. For non native types, just basic
|
||||
; Check vector comparisons using altivec. For non-native types, just basic
|
||||
; comparison instruction check is done. For altivec supported type (16i8,
|
||||
; 8i16, 4i32, and 4f32) all the comparisons operators (==, !=, >, >=, <, <=)
|
||||
; are checked.
|
||||
|
||||
@ -100,7 +100,7 @@ entry:
|
||||
ret <8 x i16> %K
|
||||
}
|
||||
|
||||
; non splat test
|
||||
; non-splat test
|
||||
|
||||
|
||||
define <8 x i16> @sll8_nosplat(<8 x i16> %A) nounwind {
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
.weak foo
|
||||
.long foo
|
||||
|
||||
// And that bar is after all local symbols and has non zero value.
|
||||
// And that bar is after all local symbols and has non-zero value.
|
||||
.weak bar
|
||||
bar:
|
||||
|
||||
|
||||
@ -28,7 +28,7 @@ Or in an archive with no symtab or string table.
|
||||
RUN: llvm-nm %p/Inputs/archive-test.a-gnu-minimal
|
||||
|
||||
|
||||
And don't crash when asked to print a non existing symtab.
|
||||
And don't crash when asked to print a non-existing symtab.
|
||||
RUN: llvm-nm -s %p/Inputs/archive-test.a-gnu-minimal
|
||||
|
||||
Don't reject an empty archive.
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; No arguments means internalize everything
|
||||
; RUN: opt < %s -internalize -S | FileCheck --check-prefix=ALL %s
|
||||
|
||||
; Non existent files should be treated as if they were empty (so internalize
|
||||
; Non-existent files should be treated as if they were empty (so internalize
|
||||
; everything)
|
||||
; RUN: opt < %s -internalize -internalize-public-api-file /nonexistent/file 2> /dev/null -S | FileCheck --check-prefix=ALL %s
|
||||
|
||||
|
||||
@ -34,7 +34,7 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
|
||||
ret void
|
||||
}
|
||||
|
||||
; Can't vectorize this loop because the access to A[X] is non linear.
|
||||
; Can't vectorize this loop because the access to A[X] is non-linear.
|
||||
;
|
||||
; for (i = 0; i < n; ++i) {
|
||||
; A[B[i]]++;
|
||||
|
||||
@ -11,8 +11,8 @@
|
||||
// llvm-config wants to report to the user, but which can only be determined at
|
||||
// build time.
|
||||
//
|
||||
// The non .in variant of this file has been autogenerated by the LLVM build. Do
|
||||
// not edit!
|
||||
// The variant of this file not ending with .in has been autogenerated by the
|
||||
// LLVM build. Do not edit!
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
@ -289,7 +289,7 @@ protected:
|
||||
struct LoadModifier: public Modifier {
|
||||
LoadModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
|
||||
virtual void Act() {
|
||||
// Try to use predefined pointers. If non exist, use undef pointer value;
|
||||
// Try to use predefined pointers. If non-exist, use undef pointer value;
|
||||
Value *Ptr = getRandomPointerValue();
|
||||
Value *V = new LoadInst(Ptr, "L", BB->getTerminator());
|
||||
PT->push_back(V);
|
||||
@ -299,7 +299,7 @@ struct LoadModifier: public Modifier {
|
||||
struct StoreModifier: public Modifier {
|
||||
StoreModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
|
||||
virtual void Act() {
|
||||
// Try to use predefined pointers. If non exist, use undef pointer value;
|
||||
// Try to use predefined pointers. If non-exist, use undef pointer value;
|
||||
Value *Ptr = getRandomPointerValue();
|
||||
Type *Tp = Ptr->getType();
|
||||
Value *Val = getRandomValue(Tp->getContainedType(0));
|
||||
|
||||
@ -116,7 +116,7 @@ public:
|
||||
ColFields = MapRec->getValueAsListInit("ColFields");
|
||||
|
||||
// Values for the fields/attributes listed in 'ColFields'.
|
||||
// Ex: KeyCol = 'noPred' -- key instruction is non predicated
|
||||
// Ex: KeyCol = 'noPred' -- key instruction is non-predicated
|
||||
KeyCol = MapRec->getValueAsListInit("KeyCol");
|
||||
|
||||
// List of values for the fields/attributes listed in 'ColFields', one for
|
||||
|
||||
Loading…
Reference in New Issue
Block a user